Abstract: In a bending region provided in a frame region, an opening is formed in an inorganic layered film, a plurality of residual layers of the inorganic layered film are provided in island shapes in a plan view in the opening, and a frame wiring line is disposed between the adjacent residual layers.

Abstract: Provided is an organic EL display device including a resin substrate layer, a TFT layer provided on the resin substrate layer, and a light-emitting element that is provided on the TFT layer and constitutes a display region. The resin substrate layer includes a first resin layer, an inorganic layer, and a second resin layer, which are provided in that order from a side opposite to the TFT layer. The interior of the first resin layer contains a plurality of air bubbles.

Abstract: In a bending region in a frame region, a slit is formed in at least one inorganic film included in a TFT layer extending through the inorganic film and exposing an upper surface of a second resin film of a resin substrate layer, and at least one opening is formed in an inorganic insulating film of the resin substrate layer in the bending region. In the opening, a first resin film and the second resin film are in contact with one another.

Abstract: Provided is a touch-panel-equipped display device that can achieve a desired touch detection performance even if it has a large-size high-definition panel. The touch-panel-equipped display device of the present invention includes an active matrix substrate (1). The active matrix substrate (1) includes, on a substrate (40), a plurality of pixel electrodes, a plurality of counter electrodes (21), and an insulating film (46) provided between the pixel electrodes and the counter electrodes (21). The active matrix substrate (1) further includes a plurality of signal lines (22) each of which is connected with any one of the counter electrodes (21), a plurality of switching elements that are connected with the pixel electrodes, respectively, and an organic insulating film (45) that is provided between the pixel electrodes and the signal lines (22) as well as the switching elements. The signal lines (22) are in contact with the substrate (40).

Abstract: Provided is a touch-panel-equipped display device that can achieve a desired touch detection performance even if it has a large-size high-definition panel. The touch-panel-equipped display device of the present invention includes an active matrix substrate (1). The active matrix substrate (1) includes, on a substrate (40), a plurality of pixel electrodes, a plurality of counter electrodes (21), and an insulating film (46) provided between the pixel electrodes and the counter electrodes (21). The active matrix substrate (1) further includes a plurality of signal lines (22) each of which is connected with any one of the counter electrodes (21), a plurality of switching elements that are connected with the pixel electrodes, respectively, and an organic insulating film (45) that is provided between the pixel electrodes and the signal lines (22) as well as the switching elements. The signal lines (22) are in contact with the substrate (40).

Abstract: In a bending region provided in a frame region, an opening is formed in an inorganic layered film, a plurality of residual layers of the inorganic layered film are provided in island shapes in a plan view in the opening, and a frame wiring line is disposed between the adjacent residual layers.

Abstract: In a bending region in a frame region, a slit is formed in at least one inorganic film included in a TFT layer extending through the inorganic film and exposing an upper surface of a second resin film of a resin substrate layer, and at least one opening is formed in an inorganic insulating film of the resin substrate layer in the bending region. In the opening, a first resin film and the second resin film are in contact with one another.

Abstract: Provided is an organic EL display device including a resin substrate layer, a TFT layer provided on the resin substrate layer, and a light-emitting element that is provided on the TFT layer and constitutes a display region. The resin substrate layer includes a first resin layer, an inorganic layer, and a second resin layer, which are provided in that order from a side opposite to the TFT layer. The interior of the first resin layer contains a plurality of air bubbles.

Abstract: Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.

Abstract: A display device according to an aspect of the present invention includes a plurality of connection terminals and a plurality of lead lines, and the plurality of lead lines includes first lead lines, second lead lines, and third lead lines. Signal-line-side first lead lines are formed of a first conductive layer, signal-line-side second lead lines are formed of a second conductive layer, and signal-line-side third lead lines are formed of a third conductive layer. A lowest conductive layer of each switching element is formed of the second conductive layer. Among the plurality of lead lines, the connection-terminal-side first lead lines, the connection-terminal-side second lead lines, and the connection-terminal-side third lead lines are formed of conductive layers that include at least the third conductive layer but do not include the first conductive layer.

Abstract: A display device according to an aspect of the present invention includes a plurality of connection terminals and a plurality of lead lines, and the plurality of lead lines includes first lead lines, second lead lines, and third lead lines. Signal-line-side first lead lines are formed of a first conductive layer, signal-line-side second lead lines are formed of a second conductive layer, and signal-line-side third lead lines are formed of a third conductive layer. A lowest conductive layer of each switching element is formed of the second conductive layer. Among the plurality of lead lines, the connection-terminal-side first lead lines, the connection-terminal-side second lead lines, and the connection-terminal-side third lead lines are formed of conductive layers that include at least the third conductive layer but do not include the first conductive layer.

Abstract: A display device according to an aspect of the present invention includes a first substrate, a second substrate, a liquid crystal layer, a plurality of signal lines, a plurality of switching elements, a plurality of connection terminals, and a plurality of lead lines. The plurality of lead lines include: first lead lines formed of a first conductive layer; second lead lines formed of a second conductive layer provided on a first insulating film covering the first lead lines; and third lead lines formed of a third conductive layer provided on a second insulating film covering the second lead lines. Among a plurality of conductive layers forming the switching elements, the lowest conductive layer is formed of the second conductive layer.

Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).

Abstract: Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.

Abstract: This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole.

Abstract: A display device according to an aspect of the present invention includes a first substrate, a second substrate, a liquid crystal layer, a plurality of signal lines, a plurality of switching elements, a plurality of connection terminals, and a plurality of lead lines. The plurality of lead lines include: first lead lines formed of a first conductive layer; second lead lines formed of a second conductive layer provided on a first insulating film covering the first lead lines; and third lead lines formed of a third conductive layer provided on a second insulating film covering the second lead lines. Among a plurality of conductive layers forming the switching elements, the lowest conductive layer is formed of the second conductive layer.

Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).

Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).

Abstract: A liquid crystal panel includes an array substrate, a row control circuit, a first trace, a second trace, a gate insulating film, and an organic insulating film. The array substrate 11b includes a display area and a non-display area. The row control circuit is arranged in the non-display area. The first trace is a component of the row control circuit. The second trace is a component of the row control circuit and arranged over the first trace so as to cross the first trace. The gate insulating film is arranged between the first trace and the second trace. The organic insulating film includes a hole formed in an area that overlaps at least crossing portions of the first trace and the second trace. The organic insulating film is made of organic resin.

Abstract: The array board 11b includes a first diode 29, a common line 25, a first shorting line 31, and the static protection portion 51. The first diode 29 include at least the first semiconductor portion 29d having outer edges 29d1 that cross the outer edges 29a1, 29b1 of first electrodes 29a, 29b in a plan view. The common line 25 is formed from the first metal film 34. The first shorting line 31 is formed from the second metal film 38 and crosses the common line 25. The static protection portion 51 is formed from the second metal film 38 or the protection film 37. At least a portion of the static protection portion 51 overlaps the common line 25 in a plan view. The static protection portion 51 is arranged closer to the first diode 29 than an intersection CPT of the common line 25 and the first shorting line 31. The static protection portion 51 includes at least a static dissipating portion 52 for dissipating static.