Abstract: A metal fabric (10) has a sheet form, using metal threads for warp (30) as the warp, and metal threads for weft (20) as the weft, wherein each of the metal threads for warp (30) and the metal threads for weft (20) has an average diameter of 0.03 mm or larger and 0.09 mm or smaller, the metal threads for warp (30) and the metal threads for weft (20) may be plain-woven, and the metal fabric (10) may be shaped in a square with a side of 100 mm or longer and 200 mm or shorter.

Abstract: There is provided a voltage detecting device. A plurality of detecting units are configured to detect voltages of a plurality of battery stacks of a battery pack having the plurality of battery stacks each having a plurality of battery cells connected, at intervals of a predetermined period, respectively. A mode switching unit is configured to perform switching between an active mode in which the detecting units detect the voltages and a standby mode in which the value of an electric current flowing in the detecting units is smaller than a predetermined value. A timing changing unit is configured to change start timings or/and finish timings of the active mode.

Abstract: A metal fabric (10) uses warp metal wires (40) as the warp, and weft metal wires (50) as the weft, where the warp metal wires (40) and the weft metal wires (50) are composed of different metal materials. A curtain (100) as an interior decoration uses the metal fabric (10). A partition member (200) is configured to have the metal fabric (10) and a frame (210) which supports the outer circumference of the metal fabric (10). A clothing is configured to contain the metal fabric (10), and an electromagnetic shielding member is configured to contain the metal fabric (10).

Abstract: Novel indansulfamide derivatives or a pharmaceutically acceptable salt thereof such as N-[(1S)-2,2,5,7-tetrafluoro-2,3-dihydro-1H-inden-1-yl]sulfamide, N-[(1S)-2,2,4,7-tetrafluoro-2,3-dihydro-1H-inden-1-yl]sulfamide, (+)-N-(2,2,4,6,7-pentafluoro-2,3-dihydro-1H-inden-1-yl)sulfamide, have an action of improving Seizure Severity Index (Score) in mice kindling model. Thus the compounds or the salt thereof are expected as a drug for treating epilepsy.

Abstract: According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1<=s<t). The search processing unit calculates the root of the error position polynomial, with a concurrency of computation being “1”, when the number of error bits exceeds the predetermined value s.

Abstract: According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1<=s<t). The search processing unit calculates the root of the error position polynomial, with a concurrency of computation being “1”, when the number of error bits exceeds the predetermined value s.

Abstract: According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.

Abstract: Novel indansulfamide derivatives or a pharmaceutically acceptable salt thereof such as N-[(1S)-2,2,5,7-tetrafluoro-2,3-dihydro-1H-inden-1-yl]sulfamide, N-[(1S)-2,2,4,7-tetrafluoro-2,3-dihydro-1H-inden-1-yl]sulfamide, (+)-N-(2,2,4,6,7-pentafluoro-2,3-dihydro-1H-inden-1-yl)sulfamide, have an action of improving Seizure Severity Index (Score) in mice kindling model. Thus the compounds or the salt thereof are expected as a drug for treating epilepsy.

Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.

Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Abstract: According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.

Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Abstract: A memory card according to an embodiment includes: a memory section having a binary storage area (SLC area) and a multi-value storage area (MLC area); an error correction section configured to correct an error of data stored in the MLC area; and an erasure correction section configured to store, in the SLC area, the position information on the multi-value memory cell storing the data having the error detected by the error correction section and configured to perform erasure correction on the basis of the position information.

Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.

Abstract: An error detector/corrector includes an ECC cache unit configured to store an error bit address which represents an error location by associating the error bit address with an error page address and a coefficient ? of an error location polynomial; a comparison unit configured to check for a match by comparing new values with stored values, where the new values are an error page address detected by a syndrome calculation unit and a coefficient ? of the error location polynomial calculated by a polynomial calculation unit while the stored values are an error page address and a coefficient ? of the error location polynomial stored in the ECC cache unit; and a first error localization unit configured to identify a location of the error bit address stored in the ECC cache unit as the error location when the comparison unit determines that the compared values match.

Abstract: A communication conversion apparatus achieve efficient conversion without conversion delay and converts messages that effect communication with different communication protocols and schedules. In a message conversion apparatus that performs message conversion of different communication protocols, a routing circuit and a scheduler circuits that perform scheduling of the different communication protocols are separately provided. And time-triggered scheduling and event-triggered scheduling are separately performed. Conversion of FlexRay and CAN messages can be efficiently implemented.

Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.

Abstract: A pump body includes a cylindrical first case for housing the plurality of rotary pumps, a second case located coaxially with the first case, and a disk spring located between the first case and the second case. In addition, a fixing means located at an entrance of the concave portion of a housing presses the second case in the insertion direction of the pump body and fixes the second case.