Abstract: A battery terminal includes: a main body unit; a penetration member that is arranged in a manner extending from an end side of the main body unit to the other end side of the main body unit across slits along a tightening direction Y, includes an abutting portion formed in the end side, and has a threaded hole and a taper forming end portion provided with first tapered surfaces formed in the other end side; a fastening member threadedly engaged with the threaded hole; and a pressing force converting member that converts fastening force in an axial direction X generated between the fastening member and the penetration member with rotation of the fastening member around the axial direction X into pressing force in the tightening direction Y pressing the main body unit between the abutting portion and the pressing force converting member along the tightening direction Y.

Abstract: A battery terminal includes: a main body unit; a penetration member that is arranged in a manner extending from an end side of the main body unit to the other end side of the main body unit across slits along a tightening direction Y, includes an abutting portion formed in the end side, and has a threaded hole and a taper forming end portion provided with first tapered surfaces formed in the other end side; a fastening member threadedly engaged with the threaded hole; and a pressing force converting member that converts fastening force in an axial direction X generated between the fastening member and the penetration member with rotation of the fastening member around the axial direction X into pressing force in the tightening direction Y pressing the main body unit between the abutting portion and the pressing force converting member along the tightening direction Y.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: [Object]

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The pad section 30A includes a wetting layer 32 and a metal wiring layer 37. The metal wiring layer 37 includes an alloy layer 34 that contacts the wetting layer 32. The alloy layer 34 is formed from a material composing the wetting layer 32 and a material composing the metal wiring layer 37.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: The invention provide highly reliable semiconductor devices that realize further miniaturization and higher density. The invention also provides methods for manufacturing such semiconductor devices. A semiconductor device in accordance with the present invention includes a first semiconductor chip disposed face-down on a surface of a tape substrate, and a second semiconductor chip disposed face-up on a rear surface of the first semiconductor chip. The semiconductor device is equipped with a wiring pattern formed on a surface of the tape substrate, solder bumps formed on a rear surface of the tape substrate, solder balls of the first semiconductor chip connected to the wiring pattern, bonding pads formed on a surface of the second semiconductor chip, bonding wires that connect the bonding pads and the wiring pattern, and a resin that seals the surface of the tape substrate, the bonding wires, and the first and second semiconductor chips.

Abstract: The invention provides a capacitance element, its manufacturing method, a semiconductor device and its manufacturing method in which ferroelectric films can be readily processed, the generation of voids in dielectric films is restrained, and the coverage of films above the capacitance elements are enhanced. A method for manufacturing a capacitor element in accordance with the present invention includes: forming a bottom electrode on an element isolation film, forming a first interlayer dielectric film on the bottom electrode, forming trenches located on the bottom electrode in the first interlayer dielectric film, depositing a ferroelectric film in the trenches and on the first interlayer dielectric film, depositing a conductive film on the ferroelectric film and in the trenches, and embedding ferroelectric films and top electrodes in the trenches by polishing the conductive film, the ferroelectric film and the first interlayer dielectric film by a CMP method.

Abstract: A semiconductor device has a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. The semiconductor device is manufactured by a method including the steps for forming an interlayer dielectric film having an internal compression stress and an interlayer dielectric film having an internal tensile stress. As a result, when semiconductor devices are manufactured, the tensile stress and the compression stress act on the semiconductor wafer. As a consequence, the overall stress that acts on the semiconductor wafer are reduced to a small level or to zero, and thus warping of the semiconductor wafer is reduced or eliminated when semiconductor devices are manufactured.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: The invention provide highly reliable semiconductor devices that realize further miniaturization and higher density. The invention also provides methods for manufacturing such semiconductor devices. A semiconductor device in accordance with the present invention includes a first semiconductor chip disposed face-down on a surface of a tape substrate, and a second semiconductor chip disposed face-up on a rear surface of the first semiconductor chip. The semiconductor device is equipped with a wiring pattern formed on a surface of the tape substrate, solder bumps formed on a rear surface of the tape substrate, solder balls of the first semiconductor chip connected to the wiring pattern, bonding pads formed on a surface of the second semiconductor chip, bonding wires that connect the bonding pads and the wiring pattern, and a resin that seals the surface of the tape substrate, the bonding wires, and the first and second semiconductor chips.

Abstract: The invention provides a highly reliable, small sized stacked level semiconductor device with high density at low costs, and also methods for manufacturing the same. The semiconductor device can include a second semiconductor chip that is disposed on a surface of a first semiconductor chip. The semiconductor device can also include metal posts for taking out electrodes formed on a surface of the first semiconductor chip, metal posts for taking out electrodes formed on a surface of the second semiconductor chip, and a resin that seals the surface of the first semiconductor chip, the metal posts, the second semiconductor chip and the metal posts. Accordingly, the present invention can provide highly reliable, small sized stacked level semiconductor devices at low costs.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: A semiconductor device has a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. The semiconductor device is manufactured by a method including the steps for forming an interlayer dielectric film having an internal compression stress and an interlayer dielectric film having an internal tensile stress. As a result, when semiconductor devices are manufactured, the tensile stress and the compression stress act on the semiconductor wafer. As a consequence, the overall stress that acts on the semiconductor wafer are reduced to a small level or to zero, and thus warping of the semiconductor wafer is reduced or eliminated when semiconductor devices are manufactured.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: An interlayer dielectric film is formed over a semiconductor substrate that may have a device element formed thereon. The interlayer dielectric film includes at least a first silicon oxide film and a second silicon oxide film as a cap layer being formed on the first silicon oxide film. The first silicon oxide film is formed by reacting SiH4 and H2O2 by a CVD method. The first silicon oxide film and the second silicon oxide film may be isotropically etched to form a through hole. The isotropic etching speed for the first silicon oxide film is the same as or generally the same as the etching speed for the second silicon oxide film (the cap layer). As a result, both the first silicon oxide film and the second silicon oxide film can be isotropically etched without causing excessive etching on the first silicon oxide film Therefore, the degree of freedom in isotropic etching is improved in isotropically etching multiple layers.