Patents by Inventor Yukio Nakabayashi

Yukio Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120228631
    Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon ca
    Type: Application
    Filed: August 25, 2011
    Publication date: September 13, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi KONO, Yukio Nakabayashi, Takashi Shinohe, Makoto Mizukami
  • Publication number: 20120146053
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.
    Type: Application
    Filed: September 20, 2011
    Publication date: June 14, 2012
    Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi, Kensuke Ota
  • Publication number: 20120146114
    Abstract: A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 14, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio NAKABAYASHI, Toshinori Numata
  • Publication number: 20120075928
    Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i?1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun Fujiki, Kiwamu Sakuma, Naoki Yasuda, Yukio Nakabayashi, Masumi Saitoh
  • Publication number: 20110303972
    Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
    Type: Application
    Filed: April 7, 2011
    Publication date: December 15, 2011
    Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi
  • Patent number: 7781274
    Abstract: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: August 24, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Ken Uchida
  • Publication number: 20090242986
    Abstract: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.
    Type: Application
    Filed: September 15, 2008
    Publication date: October 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio NAKABAYASHI, Ken UCHIDA
  • Patent number: 7521752
    Abstract: It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 21, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Kinoshita, Junji Koga, Yukio Nakabayashi
  • Patent number: 7479674
    Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: January 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
  • Publication number: 20080237655
    Abstract: A semiconductor apparatus includes: a support substrate made of a semiconductor; an insulating layer provided on the support substrate and having a first and a second openings; a semiconductor fin having a channel section, a first and second buried regions, a source section and a drain section; a gate insulating film covering a side face of the channel section; and a gate electrode opposed to the side face of the channel section across the gate insulating film. The channel section is provided upright on the insulating layer between the first and the second openings. The first and the second buried regions are provided in the first and the second openings on both sides of the channel section. The source-drain sections are provided on the first and the second buried regions and connected to the channel section.
    Type: Application
    Filed: March 24, 2008
    Publication date: October 2, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio NAKABAYASHI, Atsuhiro Kinoshita, Junji Koga
  • Publication number: 20080227241
    Abstract: A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so that the <110>directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in <110> direction to the upper wafer, and the other of which is equal in <110> direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 18, 2008
    Inventors: Yukio Nakabayashi, Junji Koga, Atsuhiro Kinoshita
  • Publication number: 20080150040
    Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 26, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
  • Patent number: 7358550
    Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: April 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
  • Publication number: 20060220131
    Abstract: It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions.
    Type: Application
    Filed: March 21, 2006
    Publication date: October 5, 2006
    Inventors: Atsuhiro Kinoshita, Junji Koga, Yukio Nakabayashi
  • Publication number: 20060199310
    Abstract: A semiconductor integrated circuit includes a substrate having a main surface to which a first stress is applied; a first channel conductive field effect transistor placed in a first region of the main surface of the substrate, the carrier mobility of a channel of the first channel conductive field effect transistor being improved by the first stress; and a second channel conductive field effect transistor placed in a second region of the main surface of the substrate, and receiving a second stress at a channel thereof, the second stress being opposite to the first stress, the carrier mobility of the channel of the second channel conductive field effect transistor being improved by the second stress, and the second region being independent from the first region.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 7, 2006
    Inventors: Yukio Nakabayashi, Junji Koga
  • Publication number: 20050212055
    Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
    Type: Application
    Filed: March 16, 2005
    Publication date: September 29, 2005
    Inventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
  • Patent number: 6835600
    Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: December 28, 2004
    Assignee: Matsushita Electric Industrial Co., LTD
    Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
  • Publication number: 20030203541
    Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.
    Type: Application
    Filed: May 16, 2003
    Publication date: October 30, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
  • Patent number: 6603194
    Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: August 5, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
  • Publication number: 20020109973
    Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.
    Type: Application
    Filed: June 13, 2001
    Publication date: August 15, 2002
    Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi