Abstract: The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data.

Abstract: First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.

Abstract: A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.

Abstract: A controller included in a flash memory system, which can be applied to a memory interface of a host computer is disclosed. A buffer is used for data exchange operation between the host computer and the controller, and data exchange operation between a flash memory and the controller. A host interface control block as a first control block controls data exchange operation between the buffer and the host computer. A flash sequencer block as a second control block controls data exchange operation between the buffer and the flash memory. The host interface control block controls input and output operation of the buffer, based on a memory control signal and a memory address signal supplied from the host computer. The flash sequencer block controls input and output operation of the buffer at a one-page size of the flash memory.

Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.

Abstract: A controller included in a flash memory system, which can be applied to a memory interface of a host computer is disclosed. A buffer is used for data exchange operation between the host computer and the controller, and data exchange operation between a flash memory and the controller. A host interface control block as a first control block controls data exchange operation between the buffer and the host computer. A flash sequencer block as a second control block controls data exchange operation between the buffer and the flash memory. The host interface control block controls input and output operation of the buffer, based on a memory control signal and a memory address signal supplied from the host computer. The flash sequencer block controls input and output operation of the buffer at a one-page size of the flash memory.

Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed.

Abstract: A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.

Abstract: A memory controller which performs a verification of the state of the erased block is performed prior to the writing operation is disclosed. The memory controller according to said present invention further performs a test operation to judge whether the erased block is a defective block to be disposed or not if the erased block is concluded to be not prefer to store data during the verification. In the case where the block is concluded to be a defective block with a permanent error by the test operation, the block is inhibited to use. In the case where the block is concluded to be a defective block with a transient error by the test operation, on the other hand, the block is treated as new erased block.

Abstract: The present invention relates to a PC card detachably installed and used for an information processing device such as a personal computer, digital-still-camera and so on to process a variety of information and its objects is to provide a PC card connectable to a plurality of information processing devices without losing the advantages of easy detachability, flexibility and portability originally owned by the PC card. A structure is formed to provide a first interface section 100 to execute data transfer between a function block supplying a predetermined function for information processing device and a portable PC (omitted in FIG. 1), and a second interface section 101 having a different interface specification from the first interface section to transfer data between the function block 2 and a desktop PC 10.

Abstract: A memory controller having an address translation table whose memory capacity is reduced is disclosed. The memory controller according to the present invention has an address translation table 27 composed of scopes 0 to 3 and a management table 28 indicating that each of the scopes 0 to 3 storing which area's address translating information. One of the scopes 0 to 3 is selected based on upper 5 bits of a host address supplied from a host computer. A logical block address included in the host address is converted into a physical block address with reference to address translating information stored in the selected scope.

Abstract: A memory controller which performs a verification of the state of the erased block is performed prior to the writing operation is disclosed. The memory controller according to said present invention further performs a test operation to judge whether the erased block is a defective block to be disposed or not if the erased block is concluded to be not prefer to store data during the verification. In the case where the block is concluded to be a defective block with a permanent error by the test operation, the block is inhibited to use. In the case where the block is concluded to be a defective block with a transient error by the test operation, on the other hand, the block is treated as new erased block.

Abstract: A flash memories (20, 21) are coupled with a host computer (1) through a flash memory controller (2) which has a pair of data buses (27, 28), and a pair of buffer memories (22, 23). Each of said data buses is coupled with a related flash memory, and a related buffer memory, which is coupled with said host computer. Said data buses (22, 23) are controlled to operate simultaneously so that said flash memories are accessed simultaneously in parallel form. A data in said host computer is transferred to said flash memories through said buffer memories and said data buses, and vice versa. All the elements (20, 21, 2) are mounted on a plastics card (100) called a flash memory card, which is coupled with a host computer through a connector. Because of use of a plurality of buses operating in parallel form, the transfer time of data between a host computer and a flash memory card is shortened.