Patents by Inventor Yuli Kh. Sakhin
Yuli Kh. Sakhin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8261250Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.Type: GrantFiled: January 10, 2011Date of Patent: September 4, 2012Assignee: Elbrus InternationalInventors: Boris A. Babaian, Yuli Kh. Sakhin, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov, Leonid N. Nazarov, Mikhail L. Chudakov
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Publication number: 20110107067Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicant: Elbrus InternationalInventors: Boris A. Babaian, Yuli Kh. Sakhin, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov, Leonid N. Nazarov, Mikhail L. Chudakov
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Patent number: 7895587Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.Type: GrantFiled: September 8, 2006Date of Patent: February 22, 2011Assignee: Elbrus InternationalInventors: Boris A. Babaian, Yuli Kh. Sakhin, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov, Leonid N. Nazarov, Mikhail L. Chudakov
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Patent number: 7143401Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.Type: GrantFiled: February 20, 2001Date of Patent: November 28, 2006Assignee: Elbrus InternationalInventors: Boris A. Babaian, Yuli Kh. Sakhin, Vladimir Yu. Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov, Leonid N. Nazarov, Mikhail L. Chudakov
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Publication number: 20010042189Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.Type: ApplicationFiled: February 20, 2001Publication date: November 15, 2001Inventors: Boris A. Babaian, Yuli Kh Sakhin, Vladimir Yu Volkonskiy, Sergey A. Rozhkov, Vladimir V. Tikhorsky, Feodor A. Gruzdov, Leonid N. Nazarov, Mikhail L. Chudakov
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Patent number: 5983336Abstract: An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided into groups of syllables. An unpacked instruction representation includes a plurality of syllables, which generally correspond to operations for execution by an execution unit. The syllables in the unpacked instruction representation are assigned to groups. The packed instruction word includes a sequence of syllables and a header. The header includes a descriptor for each group. The descriptor includes a mask and may include a displacement designator. The multiple groups are handled in parallel as the displacement designator identifies a starting syllable. The mask designates the syllables which are transferred from the packed instruction to the unpacked representation and identifies the position of NOPs in the unpacked representation.Type: GrantFiled: October 18, 1996Date of Patent: November 9, 1999Assignee: Elbrush International LimitedInventors: Yuli Kh. Sakhin, Alexander M. Artyomov, Alexey P. Lizorkin, Vladimir V. Rudometov, Leonid N. Nazarov
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Patent number: 5958048Abstract: For certain classes of software pipelined loops, prologue and epilogue portions of adjacent inner loops in a nested loop can be overlapped. In this way, outer loop code, as well as inner loop code, can be software pipelined. Architectural support for software pipelined nested loops is provided by a set of loop parameter and status registers and by an implementation of loop state dependent, multiway control transfers. For loop body code compatible with two simple constraints, the present invention does not require additional code elements for disabling garbage operations during prologue and epilogue loop periods of adjacent inner loops. Nested loop control allows overlap between the epilogue period of a prior inner loop and the prologue period of a next inner loop. As a result, nested loop code can be more efficiently scheduled by a compiler for execution on a processor such as VLIW processor which provides architectural support for software pipelined nested loops, thereby providing improved loop performance.Type: GrantFiled: October 18, 1996Date of Patent: September 28, 1999Assignee: Elbrus International Ltd.Inventors: Boris A. Babaian, Feodor A. Gruzdov, Yuli Kh. Sakhin, Vladimir S. Volin, Vladimir Yu. Volkonski
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Patent number: 5889985Abstract: An array prefetch system improves processor performance by automatically tuning a statically compiled and compacted loop program at run-time to accommodate variations in latency of memory read operations. Using the array prefetch system, the processor, while awaiting completion of a data access, continues to generate requests for subsequent iterations rather than fully halting execution until a read access is finished.Type: GrantFiled: October 18, 1996Date of Patent: March 30, 1999Assignee: Elbrus InternationalInventors: Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Yuli Kh. Sakhin, Vladimir Yu. Volkonski
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Patent number: 5794029Abstract: For certain classes of software pipelined loops, prologue and epilogue control is provided by loop control structures, rather than by predicated execution features of a VLIW architecture. For loops compatible with two simple constraints, code elements are not required for disabling garbage operations during prologue and epilogue loop periods. As a result, resources associated with implementation of the powerful architectural feature of predicated execution need not be squandered to service loop control. In particular, neither increased instruction width nor an increased number of instructions in the loop body is necessary to provide loop control in accordance with the present invention. Fewer service functions are required in the body of a loop. As a result, loop body code can be more efficiently scheduled by a compiler and, in some cases, fewer instructions will be required, resulting in improved loop performance.Type: GrantFiled: October 18, 1996Date of Patent: August 11, 1998Assignee: Elbrus International Ltd.Inventors: Boris A. Babaian, Valeri G. Gorokhov, Feodor A. Gruzdov, Yuli Kh. Sakhin, Vladimir Yu. Volkonski