Patents by Inventor Yumi Nakajima

Yumi Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10877375
    Abstract: A reflection type exposure mask includes a substrate, a reflective layer provided on the substrate, and a light absorption layer provided on the surface of the reflective layer. The light absorption layer includes a first absorber and a second absorber. The first absorber extends in a first direction along the surface of the reflective layer. The second absorber extends in a second direction along the surface of the reflective layer, which intersects with the first direction. The thickness of the second absorber in a third direction which is perpendicular to the surface of the reflective layer is thinner than the thickness of the first absorber in the third direction.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yumi Nakajima
  • Patent number: 10771851
    Abstract: An information processing apparatus receives a user selection of content to be reproduced by an external device connected to the information processing apparatus. A request to reproduce the user selected content is sent to the external device. Information indicating whether the external device has started reproducing the selected content is received from the external device. In response to the external device having started reproduction of the selected content, a thumbnail image is reproduced that corresponds to the content being reproduced by the external device.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 8, 2020
    Assignee: Sony Corporation
    Inventors: Satoshi Hiroi, Yukio Ichikawa, Yumi Sato, Marie Suzuki, Yasushi Nakajima, Hiroshi Nagatani, Masahiro Hara, Hiroshi Horiki, Kouhei Fujimoto, Takeshi Matsuzawa, Hiroyuki Mitsubori, Sakae Houjou, Mingshan Yang
  • Publication number: 20200176434
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Yumi NAKAJIMA
  • Patent number: 10600771
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Iijima, Yumi Nakajima
  • Publication number: 20200075622
    Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.
    Type: Application
    Filed: February 25, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro FUJII, Satoshi NAGASHIMA, Yumi NAKAJIMA
  • Publication number: 20190287955
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Yumi NAKAJIMA
  • Publication number: 20190254316
    Abstract: The present invention relates to a browning-inhibiting composition containing a compound represented by the following formula (1): wherein R21, R22, R23, R24, R26 and R27 each independently represent a hydrogen atom or a substituent, and at least one of R21 or R23 is a hydrogen atom; when R23 represents a hydrogen atom, at least one of R22 or R24 represents a substituent; R25 represents a hydrogen atom, an oxygen atom, or a substituent; R22 and R23, or R23 and R24 may be bonded together to form a ring with an oxygen atom and a carbon atom to which these Rs are bonded; R25 and R26, or R26 and R27 may be bonded together to form a ring structure with carbon atoms to which these Rs are bonded; X represents an oxygen atom or —CH2—; and a dashed line may represent a double bond.
    Type: Application
    Filed: June 23, 2017
    Publication date: August 22, 2019
    Applicant: SUNTORY HOLDINGS LIMITED
    Inventors: Suguru Nakajima, Yumi Sasanuma, Yoshihide Matsuo
  • Patent number: 10328615
    Abstract: According to one implementation, a molding equipment of a composite material includes a vessel, a decompression system and a heating medium supply system. The vessel houses a molding target sealed by a sealing object. The decompression system performs bending forming of the molding target and pressurization on the molding target after the bending forming by decompressing a region surrounded by the sealing object in the vessel. The heating medium supply system supplies a heating medium into the vessel. The heating medium is supplied for the bending forming, and heating and curing of the molding target under the pressurization.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 25, 2019
    Assignees: SUBARU CORPORATION, KABUSHIKI KAISHA ASHIDA SEISAKUSHO
    Inventors: Yumi Ito, Masanori Nakajima, Takeshi Ashida
  • Patent number: 10321017
    Abstract: An image processing apparatus according to the present invention includes an acquisition unit configured to acquire an output condition when an image forming apparatus forms an image on a recording medium based on image data, and a processing unit configured to perform image processing on the image data for improving sharpness of the image by using a parameter based on the output condition. The parameter to be referred to by the processing unit represents such a characteristic that the image formed by the image forming apparatus has a luminous characteristic in relation to spatial frequency that remains constant or decreases continuously without causing any inflection point or any discontinuous point in a frequency band from a predetermined frequency to a limit frequency of the image forming apparatus.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 11, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Naoya Takesue, Hisashi Ishikawa, Tomokazu Yanai, Hiroyuki Sakai, Yoshinori Nakajima, Hajime Nagai, Yumi Shimokodachi
  • Publication number: 20190079387
    Abstract: A reflection type exposure mask includes a substrate, a reflective layer provided on the substrate, and a light absorption layer provided on the surface of the reflective layer. The light absorption layer includes a first absorber and a second absorber. The first absorber extends in a first direction along the surface of the reflective layer. The second absorber extends in a second direction along the surface of the reflective layer, which intersects with the first direction. The thickness of the second absorber in a third direction which is perpendicular to the surface of the reflective layer is thinner than the thickness of the first absorber in the third direction.
    Type: Application
    Filed: February 27, 2018
    Publication date: March 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Yumi NAKAJIMA
  • Patent number: 9418887
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a first insulating film, forming a first mask extending in first direction on the first insulating film, etching the first insulating film using the first mask, resulting in trenches extending in a first direction, forming a second mask on the trenches and the first mask, etching the first insulating film using the second mask and the first mask to form contact openings extending from the trenches.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yumi Nakajima
  • Patent number: 9209052
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yumi Nakajima, Kentaro Matsunaga, Eiji Yoneda
  • Patent number: 9153456
    Abstract: According to one embodiment, first, on a process object, a hydrophilic guide pattern including a first hole forming pattern having a first hole diameter and a second hole forming pattern having a second hole diameter is formed. Then, above the guide pattern, a frame pattern having a first opening region in a forming region of a plurality of the first hole forming patterns and a second opening region in a forming region of a plurality of the second hole forming patterns is formed. Then, a first solution including a first block copolymer having a hydrophilic polymer chain and a hydrophobic polymer chain is supplied to the first opening region to condense the first block copolymer. The hydrophilic polymer chain is then removed to reduce the diameter of the first hole forming pattern to a third hole diameter that is smaller than the first hole diameter.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Nakajima, Kentaro Matsunaga
  • Publication number: 20150279727
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. The method includes forming a first insulating film, forming a first mask extending in first direction on the first insulating film, etching the first insulating film using the first mask, resulting in trenches extending in a first direction, forming a second mask on the trenches and the first mask, etching the first insulating film using the second mask and the first mask to form contact openings extending from the trenches.
    Type: Application
    Filed: September 2, 2014
    Publication date: October 1, 2015
    Inventor: Yumi NAKAJIMA
  • Publication number: 20140377956
    Abstract: According to one embodiment, first, on a process object, a hydrophilic guide pattern including a first hole forming pattern having a first hole diameter and a second hole forming pattern having a second hole diameter is formed. Then, above the guide pattern, a frame pattern having a first opening region in a forming region of a plurality of the first hole forming patterns and a second opening region in a forming region of a plurality of the second hole forming patterns is formed. Then, a first solution including a first block copolymer having a hydrophilic polymer chain and a hydrophobic polymer chain is supplied to the first opening region to condense the first block copolymer. The hydrophilic polymer chain is then removed to reduce the diameter of the first hole forming pattern to a third hole diameter that is smaller than the first hole diameter.
    Type: Application
    Filed: December 9, 2013
    Publication date: December 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yumi NAKAJIMA, Kentaro Matsunaga
  • Publication number: 20140227807
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values.
    Type: Application
    Filed: August 12, 2013
    Publication date: August 14, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yumi NAKAJIMA, Kentaro MATSUNAGA, Eiji YONEDA
  • Patent number: 8728711
    Abstract: In one embodiment, a method for cleaning a reticle stage of an extreme ultraviolet exposure apparatus is disclosed. The method can include pressing a particle catching layer of a cleaning reticle onto the reticle stage, and the cleaning reticle includes the particle catching layer formed on a substrate. The method can include peeling the cleaning reticle from the reticle stage. The method can include removing the particle catching layer from the substrate. I addition, the method can include forming a new particle catching layer on the substrate having the particle catching layer removed.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Nakajima, Suigen Kyoh, Ryoichi Inanami
  • Patent number: 8187773
    Abstract: A method for generating data on mask pattern used to form a device pattern formed on a reflective exposure mask, wherein data on the mask pattern is generated based on a position correction amount table used to correct an amount of transfer position error occurring depending on at least one of pattern size and pattern pitch of the mask pattern when the mask pattern is transferred onto an exposure target member.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Nakajima, Masaru Suzuki, Takashi Sato
  • Publication number: 20120068372
    Abstract: According to one embodiment, a nanoimprint template using a pattern transcription to a substrate by a nanoimprint technique, the template includes a transcription pattern and an alignment mark on a main surface of a main body, wherein the alignment mark comprises a polarizer.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 22, 2012
    Inventors: Akiko Mimotogi, Ryoichi Inanami, Kentaro Kasa, Masato Suzuki, Manabu Takakuwa, Yohko Furutono, Yumi Nakajima
  • Publication number: 20120040293
    Abstract: A reflective mask comprising: a reflective layer that is arranged on a surface on a side on which EUV light is irradiated and reflects the EUV light; a buffer layer containing Cr that is arranged on a side of the reflective layer on which the EUV light is irradiated and covers an entire surface of the reflective layer; and a non-reflective layer that is arranged on a side of the buffer layer on which the EUV light is irradiated and in which an absorber that absorbs the irradiated EUV light is arranged in a position corresponding to a mask pattern to be reduced and transferred onto a wafer.
    Type: Application
    Filed: October 27, 2011
    Publication date: February 16, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Inanami, Yumi Nakajima, Masamitsu Itoh