Patents by Inventor Yun Cheng

Yun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240280875
    Abstract: A front light module including a light guide plate, a light source, a protective cover plate, an appearance color layer, and a functional layer is provided. The light guide plate has a first surface, a second surface opposite to the first surface, and a light incident surface connecting the first surface to the second surface. The light source is disposed beside the light incident surface and configured to emit light toward the light incident surface. The protective cover plate is disposed on the first surface, and the protective cover plate has a third surface facing away from the light guide plate and a fourth surface facing the light guide plate. The appearance color layer is disposed on a portion of the third surface. The functional layer covers the appearance color layer and the third surface. An electrophoretic display device is also provided.
    Type: Application
    Filed: December 20, 2023
    Publication date: August 22, 2024
    Applicant: E Ink Holdings Inc.
    Inventors: Chih Cheng Ko, Yun-Nan Hsieh
  • Patent number: 12068371
    Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Ya-Yun Cheng, Shahaji B. More, Cheng-Yi Peng, Wei-Yang Lee, Kuo-Feng Yu, Yen-Ming Chen, Jian-Hao Chen
  • Publication number: 20240273675
    Abstract: An image calibration method is applied to an image calibration device includes an image receiver and an operation processor. The image calibration method of providing a motion deblur function includes driving a first camera to capture a first image having a first exposure time, driving a second camera disposed adjacent to the first camera to capture a second image having a second exposure time different from and at least partly overlapped with the first exposure time, and fusing a first feature of the first image and a second feature of the second image to generate a fusion image.
    Type: Application
    Filed: January 2, 2024
    Publication date: August 15, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Hua Huang, Pin-Wei Chen, Keh-Tsong Li, Shao-Yang Wang, Chia-Hui Kuo, Hung-Chih Ko, Yun-I Chou, Yen-Yang Chou, Chien-Ho Yu, Chi-Cheng Ju, Ying-Jui Chen
  • Publication number: 20240263988
    Abstract: A liquid level gauge and waveguide set includes a liquid level gauge installed on a vertical wall of a sewer, so that the liquid level detection module of the liquid level gauge emits radar waves or ultrasonic waves toward a sewage pipeline buried in a ditch on the bottom surface of the sewer for liquid level sensing, and a waveguide fixed on the vertical wall of the sewer with one end thereof facing the liquid level detection module. The waveguide has an exhaust branch pipe extending obliquely upwards from a top wall thereof. The radar wave or ultrasonic wave emitted by the liquid level detection module is reflected by the inner wall of the waveguide and touches the liquid surface covering the periphery of the sewage pipeline, and is transmitted back through the inner wall of the waveguide to the liquid level detection module to obtain liquid level data.
    Type: Application
    Filed: February 7, 2023
    Publication date: August 8, 2024
    Inventors: Shueh-Ting LIN, Yung-Yun CHENG
  • Patent number: 12056534
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations represented as a computational graph on a distributed computing network. A method includes: receiving data representing operations to be executed in order to perform a job on a plurality of hardware accelerators of a plurality of different accelerator types; generating, for the job and from at least the data representing the operations, features that represent a predicted performance for the job on hardware accelerators of the plurality of different accelerator types; generating, from the features, a respective predicted performance metric for the job for each of the plurality of different accelerator types according to a performance objective function; and providing, to a scheduling system, one or more recommendations for scheduling the job on one or more recommended types of hardware accelerators.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: August 6, 2024
    Assignee: Google LLC
    Inventors: Sheng Li, Brian Zhang, Liqun Cheng, Norman Paul Jouppi, Yun Ni
  • Patent number: 12057504
    Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Sin Wang, Shan-Yun Cheng, Ching-Hung Kao, Jing-Jyu Chou, Yi-Ting Chen
  • Publication number: 20240254334
    Abstract: Disclosed herein are polymer compositions comprising from about 1 wt. % to about 99 wt. % of a polyetherimide resin; from about 1 wt. % to about 70 wt. % of a crystalline polyester resin; from about 0.1 wt. % to about 50 wt. % of an inherently dissipative polymer; and from about 0.001 wt. % to about 10 wt. % of a transesterification inhibitor. The combined weight percent value of all components does not exceed about 100 wt. %, and all weight percent values are based on the total weight of the polymer composition. The polymer composition may exhibit a surface resistivity of from 1×109 ohms to 9×1010 ohms when measured in accordance with ASTM D257.
    Type: Application
    Filed: May 27, 2022
    Publication date: August 1, 2024
    Inventors: Xiaoming Jiang, Yun Zheng, Yunan Cheng
  • Patent number: 12048164
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240243001
    Abstract: An apparatus includes a supporting frame, a platform supported by the supporting frame and having a first side and a second side opposite to the first side, and at least three robot fingers which are mounted to the supporting frame, and which are angularly displaced from each other. Each of the robot fingers has a fingertip configured to retain a substrate on the first side of the platform such that the substrate is spaced apart from the platform. A method for manufacturing a semiconductor structure using the apparatus is also disclosed.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yun CHENG, Kenichi SANO, Yu-Wei LU, Yi-Chen LO
  • Patent number: 12040397
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Cheng Yang, Yun-Chi Wu, Shih-Jung Tu
  • Publication number: 20240231023
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 24, 2023
    Publication date: July 11, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Publication number: 20240233564
    Abstract: A communication method in a virtual environment includes initiating, by a first user, a virtual classroom through an education Metaverse application program of a first user device; attending, by at least a second user, the virtual classroom through an education Metaverse application program of a second user device; activating, by the first user, a class teaching mode, such that the first user and at least the second user login a cloud streaming system through corresponding education Metaverse application program of the first user device and the second user device to represent a first Avatar and a second Avatar for communication in the virtual classroom; wherein the virtual classroom is configured to render a spatial audio in a three-dimensional (3D) space.
    Type: Application
    Filed: September 22, 2023
    Publication date: July 11, 2024
    Applicant: ViewSonic International Corporation
    Inventors: Ting-Ting Hsiao, Chih-Wei Lu, Po-Chun Hsu, Wen-Ju Chow, Shih-Chang Weng, Yun-Cheng Hsin, Yu-Zhen Huang
  • Publication number: 20240237207
    Abstract: A circuit board includes a substrate, an insulating structure, a pad structure and a side wire. The substrate has a first surface, a second surface opposite to the first surface, and a side surface. The insulating structure is located above the first surface of the substrate. The pad structure is located in the insulating structure. The insulating structure includes an opening on the pad structure and a removal region between the pad structure and the side surface of the substrate. At least a portion of the insulating structure in the removal region is removed, and the horizontal distance between the removal region and the pad structure is H, 0<H?10 micrometers. The side wire is filled into the opening of the insulating structure, and extends from the pad structure to the second surface of the substrate.
    Type: Application
    Filed: November 1, 2023
    Publication date: July 11, 2024
    Applicant: AUO Corporation
    Inventors: Yun Cheng, Hao-An Chuang
  • Publication number: 20240213314
    Abstract: A semiconductor device including a FET includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
    Type: Application
    Filed: January 12, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung TSAI, Chih-Hsin KO, Clement Hsing Jen WANN, Ya-Yun CHENG
  • Publication number: 20240186305
    Abstract: A device substrate, including a circuit substrate, a first side wiring, a sealant structure, and a second side wiring, is provided. The first side wiring extends from a first surface of the circuit substrate to a second surface of the circuit substrate along a side surface of the circuit substrate. The sealant structure is located above the first surface and covers the first side wiring on the first surface. The second side wiring extends from the sealant structure to the first side wiring located on the side surface and the second surface of the circuit substrate.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 6, 2024
    Applicant: AUO Corporation
    Inventors: Yun Cheng, Hsi-Hung Chen, Hao-An Chuang
  • Publication number: 20240182904
    Abstract: Provided herein are oligonucleotides (e.g., siRNA) targeting S6K1. Also provided are methods of treating a disease associated with S6K1 expression.
    Type: Application
    Filed: September 29, 2023
    Publication date: June 6, 2024
    Inventors: Claudio Punzo, Anastasia Khvorova, Dimas Echeverria Moreno, Annabelle Biscans, Julia F. Alterman, Matthew Hassler, Shun-Yun Cheng, Jillian Caiazzi
  • Publication number: 20240173420
    Abstract: Provided herein are conjugated oligonucleotides that are characterized by efficient and specific eye distribution.
    Type: Application
    Filed: September 29, 2023
    Publication date: May 30, 2024
    Inventors: Claudio Punzo, Anastasia Khvorova, Dimas Echeverria Moreno, Annabelle Biscans, Julia F. Alterman, Matthew Hassler, Shun-Yun Cheng
  • Publication number: 20240134136
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Patent number: D1024075
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Yun Cheng, Tsun-Chih Yang
  • Patent number: D1024474
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: April 23, 2024
    Inventor: Yun Cheng