Abstract: A driving device and a driving method for driving a motor of an electric auxiliary vehicle are provided. The driving device includes a battery module, a transducer, a control circuit. The battery module stores a driving power. When an acceleration command is received, the control circuit controls the transducer to enter a first mode. In the first mode, the transducer provides the driving power to the motor. When a brake command is received, the control circuit controls the transducer to enter a second mode. In the second mode, the transducer provides an inductive power generated by the motor to the battery module. When the acceleration and brake commands are not received and a user does not apply an acceleration force to the electric auxiliary vehicle, the control circuit controls the transducer to enter a third mode. In the third mode, the transducer provides the inductive power to the battery module.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: A holding device applied to a cutting apparatus to hold an object to be cut includes a holding element and a plurality of damping particles. The holding element is used for holding the object to be cut, and the holding element includes at least one accommodating cavity. Each accommodating cavity extends inward from the outer surface of the holding element to form an accommodating space. The plurality of damping particles is placed in at least one accommodating cavity. During the cutting process of the object to be cut, the plurality of damping particles generates collision and friction with each other or with the cavity wall of the accommodating cavity to reduce the vibration generated by the object to be cut, thereby reducing the surface warpage of a plurality of small-volume objects formed after cutting the object to be cut.

Abstract: Technology is disclosed for transferring money anonymously between a sender and a recipient by use of a one-time use token. The method includes generating a one-time use token account for association with a one-time use token. The method includes generating the token and providing the token to the sender device in a machine-readable and transferable format. The method includes receiving a request to charge the one-time use token account after the token has been provided to the recipient device as a form of payment for a transaction. The method includes determining that an amount of the transaction is less than an amount of funds associated with the token and that the time of the transaction is within a time period for the use of the token. The method includes facilitating a transfer to the recipient account and deducting the amount of the transaction from a sender account.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.

Abstract: A driving system for an elevator. The driving system includes a motor, a power source, a battery device, a conversion circuit, a power path circuit and a controller. The motor controls a movement of the elevator in response to a driving power. The power source provides a source power. The battery device stores a battery power. When the elevator is moving, the controller controls the power path circuit to generate a power delivering path between the conversion circuit and the motor, and controls the conversion circuit to convert the battery power into the driving power. When the elevator is at rest, the controller controls the power path circuit to generate a charging path between the conversion circuit and the power source, and controls the conversion circuit to convert the source power into the battery power.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A semiconductor device includes a dielectric structure, a conductive structure disposed in the dielectric structure, a first dielectric feature disposed over the dielectric structure, a conductive element disposed in the first dielectric feature and connected to the conductive structure, and a barrier feature disposed around the conductive element and disposed outside of the conductive structure.

Abstract: A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

Abstract: A cross laser calibration device used to calibrate a tool center point is provided. The calibration device includes a coordinate orifice plate, a set of cross laser sensors and a rotational and translational movement mechanism. The coordinate orifice plate has an orifice center point. The set of cross laser sensors is arranged on the coordinate orifice plate to generate cross laser lines intersecting at the orifice center point. The set of cross laser sensors is driven by the second motor to rotate around the center point of the second motor, wherein the orifice center point has an off-axis setting relative to the center point of the second motor.

Abstract: A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.

Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.

Abstract: An electrolyte composition, quasi-solid-state electrolyte, and lithium-ion battery employing the same are provided. The electrolyte composition includes a component (A), component (B) and component (C). The component (A) is a combination of a first polymer (A1) and a second polymer (A2), or a third polymer (A3). The first polymer (A1) has a repeating unit of Formula (I), the second polymer (A2) has a repeating unit of Formula (II), and the third polymer (A3) has a repeating unit of Formula (I) and a repeating unit of Formula (II) , wherein R1, R2, R3, R4, R5, Z1, and Z3 are as defined in the specification. The component (B) is a lithium salt and the component (C) is a solvent.