Patents by Inventor Yunfei Deng

Yunfei Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8642474
    Abstract: Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: February 4, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ryoung-han Kim, Yunfei Deng, Thomas I. Wallow, Bruno La Fontaine
  • Patent number: 8637214
    Abstract: Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 28, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Yunfei Deng, Jongwook Kye
  • Patent number: 8598633
    Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: December 3, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8581348
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Mahbub Rashed, Steven Soss, Jongwook Kye, Irene Y. Lin, James Benjamin Gullette, Chinh Nguyen, Jeff Kim, Marc Tarabbia, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20130275935
    Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain, Jongwook Kye, Ali Keshavarzi, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20130181289
    Abstract: A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Marc Tarabbia, James B. Gullette, Mahbub Rashed, David S. Doman, Irene Y. Lin, Ingolf Lorenz, Larry Ho, Chinh Nguyen, Jeff Kim, Jongwook Kye, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Jason E. Stephens, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20130146982
    Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mahbub Rashed, Steven Soss, Jongwook Kye, Irene Y. Lin, James Benjamin Gullette, Chinh Nguyen, Jeff Kim, Marc Tarabbia, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8361335
    Abstract: Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: January 29, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Yunfei Deng, Jongwook Kye
  • Publication number: 20100311242
    Abstract: Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yunfei Deng, Jongwook Kye
  • Patent number: 7829266
    Abstract: Accurate ultrafine patterns are formed using a multiple exposure technique comprising implementing an OPC procedure to form an exposure reticle to compensate for distortion of an overlying resist pattern caused by an underlying resist pattern. Embodiments include forming a first resist pattern in a first resist layer over a target layer using a first exposure reticle, forming a second exposure reticle by an OPC technique to compensate for distortion of a second resist pattern caused by the underlying first resist pattern, depositing a second resist layer on the first resist pattern, forming the second resist pattern in the second resist layer using the second exposure reticle, the first and second resist patterns constituting a final resist mask, and forming a pattern in the target layer using the final resist mask.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: November 9, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yunfei Deng, Jongwook Kye, Ryoung-han Kim
  • Patent number: 7718529
    Abstract: Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: May 18, 2010
    Assignee: GlobalFoundries Inc.
    Inventors: Yunfei Deng, Ryoung-han Kim, Thomas I. Wallow
  • Publication number: 20090040483
    Abstract: Accurate ultrafine patterns are formed using a multiple exposure technique comprising implementing an OPC procedure to form an exposure reticle to compensate for distortion of an overlying resist pattern caused by an underlying resist pattern. Embodiments include forming a first resist pattern in a first resist layer over a target layer using a first exposure reticle, forming a second exposure reticle by an OPC technique to compensate for distortion of a second resist pattern caused by the underlying first resist pattern, depositing a second resist layer on the first resist pattern, forming the second resist pattern in the second resist layer using the second exposure reticle, the first and second resist patterns constituting a final resist mask, and forming a pattern in the target layer using the final resist mask.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 12, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Yunfei Deng, Jongwook Kye, Ryoung-han Kim
  • Publication number: 20090023298
    Abstract: Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 22, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Yunfei Deng, Ryoung-han Kim, Thomas I. Wallow
  • Publication number: 20090017628
    Abstract: Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 15, 2009
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ryoung-han KIM, Yunfei Deng, Thomas I. Wallow, Bruno La Fontaine
  • Patent number: 7060401
    Abstract: A reflective reticle includes reflective regions of different phases, with one of the reflective regions being, for example, 180 degrees out of phase with another region. The reflective reticle also includes absorptive regions, which may be placed between reflective regions of opposite phases. The reticle may include a reflector, made up of multiple reflective layers, atop a substrate of absorptive material. The reflector may have some of the reflective areas removed in the phase-shift regions, and substantially all of the reflective layers removed in the absorptive regions. The reticle may allow for greater resolution extreme ultraviolet (EUV) lithography.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: June 13, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bruno M. LaFontaine, Adam R. Pawloski, Yunfei Deng