Patents by Inventor Yung-Chun Yang

Yung-Chun Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11942130
    Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
  • Publication number: 20240084454
    Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yung-Tsun LIU, Kuang-Wei CHENG, Sheng-chun YANG, Chih-Tsung LEE, Chyi-Tsong NI
  • Publication number: 20240040530
    Abstract: A method of determining UE registration status for a UE that is registered to different PLMN networks over 3GPP and non-3GPP accesses is proposed. The UE triggers registration to a second Public Land Mobile Network (PLMN) or Standalone Non-Public Network (SNPN) over a second access, and receives a REGISTRATION ACCEPT message from the second network over the second access. The REGISTRATION ACCEPT message carries a 5GS registration result IE having a 5GS registration result value. If the 5GS registration result value indicates that the UE is registered (or not registered) to a first network over a first access, then the UE may ignore the indication and considers the UE is not registered (or registered) to the first network over the first access.
    Type: Application
    Filed: July 4, 2023
    Publication date: February 1, 2024
    Inventors: Yu-Hsin Lin, Yung-Chun Yang, Yuan-Chieh Lin
  • Publication number: 20240040459
    Abstract: A method of performing intersystem change without N26 interface supported or not supported when a UE is registered to the same or different networks over 3GPP and non-3GPP accesses is proposed. UE registers to one or more PLMN/SNPN over 3GPP access and non-3GPP access. UE receives a REGISTRATION ACCEPT message over 3GPP access, which carries a first 5GS network feature support IE, which indicates that interworking without N26 interface not supported. UE also receives a REGISTRATION ACCEPT message over non-3GPP access, which carries a second 5GS network feature support IE, which indicates that interworking without N26 interface supported. UE ignores the second indication received over non-3GPP access and considers that N26 interface is supported for interworking. As a result, after intersystem change from 5G to 4G, UE triggers a TAU procedure over LTE in 4G EPS.
    Type: Application
    Filed: July 4, 2023
    Publication date: February 1, 2024
    Inventors: Yuan-Chieh Lin, Yung-Chun Yang, Yu-Hsin Lin
  • Publication number: 20240040496
    Abstract: A method of determining UE access identity for a UE that is registered to the same or different PLMN networks over 3GPP and non-3GPP accesses is proposed. The UE registers to one or more Public Land Mobile Network (PLMN) or Standalone Non-Public Network (SNPN) over 3GPP access and non-3GPP access. If the UE registers to the same PLMN/SNPN over 3GPP and non-3GPP access, then the UE handles the UE access identity as one common parameters. On the other hand, if the UE registers to different PLMN/SNPN over 3GPP and non-3GPP, then the UE handles the UE access identity as two independent parameters. The access identity may comprise a priority indicator IE that is set to “Access Identity 1 valid” for MPS or “Access Identity 2 valid” for MCS.
    Type: Application
    Filed: July 4, 2023
    Publication date: February 1, 2024
    Inventors: YUAN-CHIEH Lin, Yung-Chun Yang, Yu-Hsin Lin
  • Publication number: 20230343819
    Abstract: Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min Liu, Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo, Hui-Lin Huang
  • Publication number: 20230317785
    Abstract: A device includes a first nanostructure over a substrate and a first source/drain region adjacent the first nanostructure. The first source/drain region includes a first epitaxial layer covering a first sidewall of the first nanostructure. The first epitaxial layer has a first concentration of a first dopant. The first epitaxial layer has a round convex profile opposite the first sidewall of the first nanostructure in a cross-sectional view. The first source/drain region further includes a second epitaxial layer covering the round convex profile of the first epitaxial layer in the cross-sectional view. The second epitaxial layer has a second concentration of the first dopant, the second concentration being different from the first concentration.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Yung-Chun Yang, Wei Hao Lu, Wei-Min Liu, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Patent number: 11570616
    Abstract: Methods and apparatus are provided for providing UE EPS capability information and receiving non-access stratum (NAS) security algorithm information for an interworking procedure in the 5GS network. In one novel aspect, the UE provides the UE EPS capability information in cleartext before the security mode procedure, and the NAS security algorithm information is included in a security mode command message during the security mode procedure. In one embodiment, the UE EPS capability information is an S1 mode indicator or the 5GMM capability information including the Si mode indicator. In another novel aspect, the network provides the NAS security algorithm information before interworking procedure from 5GS to LTE. In one embodiment, the network provides the NAS security algorithm information in the Registration Accept message. In another embodiment, the network provides the NAS security algorithm information in handover procedure from the 5GS to LTE.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 31, 2023
    Assignee: MEDIATEK INC.
    Inventors: Yu-Cheng Huang, Chi-Chen Lee, Hao-Hsiang Chung, Yung-Chun Yang, Chien-Chun Huang-Fu
  • Publication number: 20230028591
    Abstract: A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.
    Type: Application
    Filed: April 4, 2022
    Publication date: January 26, 2023
    Inventors: Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20220272526
    Abstract: Methods and apparatus are provided for providing UE EPS capability information and receiving non-access stratum (NAS) security algorithm information for an interworking procedure in the 5GS network. In one novel aspect, the UE provides the UE EPS capability information in cleartext before the security mode procedure, and the NAS security algorithm information is included in a security mode command message during the security mode procedure. In one embodiment, the UE EPS capability information is an S1 mode indicator or the 5GMM capability information including the Si mode indicator. In another novel aspect, the network provides the NAS security algorithm information before interworking procedure from 5GS to LTE. In one embodiment, the network provides the NAS security algorithm information in the Registration Accept message. In another embodiment, the network provides the NAS security algorithm information in handover procedure from the 5GS to LTE.
    Type: Application
    Filed: August 7, 2020
    Publication date: August 25, 2022
    Inventors: Yu-Cheng HUANG, Chi-Chen LEE, Hao-Hsiang CHUNG, Yung-Chun YANG, Chien-Chun HUANG-FU
  • Publication number: 20180176136
    Abstract: Apparatus and methods are provided for TCP bufferbloat resolution. In one novel aspect, the TCP client monitors a TCP throughput, determines a TCP throughput stability based on a changing rate of the TCP throughput, adjusts a RWND size dynamically based on the determined TCP throughput stability, and sends the dynamically adjusted RWND size to the TCP server for flow control. In one embodiment, the TCP throughput is stable if the changing rate of an increase or decrease of the TCP throughput is smaller than a threshold, otherwise, the TCP throughput is unstable. The TCP client decreases the RWND size if the TCP throughput is stable, otherwise the TCP client increases the RWND size. In one embodiment, the increase of the RWND size uses the default RWND size adjustment method and the decrease of the RWND size is further depending on the increasing or decreasing state of the TCP client.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 21, 2018
    Inventors: Yung-Chun Yang, Cheng-Jie Tsai, Tsern-Huei Lee, Guan-Yu Lin, Yung-Hsiang Liu, Jun-Hua Chou, Chia-Chun Hsu