Patents by Inventor Yung Fu Chong

Yung Fu Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006517
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Patent number: 11855195
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 26, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Patent number: 11855196
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 26, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Publication number: 20230411208
    Abstract: Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Inventors: Wensheng Deng, Kemao Lin, Curtis Chun-I Hsieh, Wanbing Yi, Liu Xinfu, Rui Tze Toh, Yanxia Shao, Shucheng Yin, Jason Kin Wei Wong, Yung Fu Chong
  • Publication number: 20230395425
    Abstract: The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature, and a contact via structure. The conductive feature is over the substrate. The contact via structure is electrically coupled to the conductive feature and includes a curved concave profile throughout a height of the contact via structure and an upper width wider than the width of the conductive feature.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 7, 2023
    Inventors: YUNG FU CHONG, RUI TZE TOH, FANGYUE LIU
  • Patent number: 11776844
    Abstract: The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature over the substrate, and a contact via structure over and electrically coupling to the conductive feature. The contact via structure has a concave profile.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 3, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yung Fu Chong, Rui Tze Toh, Fangyue Liu
  • Publication number: 20230127768
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Publication number: 20230129914
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
  • Publication number: 20220310444
    Abstract: The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature over the substrate, and a contact via structure over and electrically coupling to the conductive feature. The contact via structure has a concave profile.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: YUNG FU CHONG, RUI TZE TOH, FANGYUE LIU
  • Patent number: 10566441
    Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Hao Nong, Liang Li, Chiew Wah Yap, Ting Huo, Yung Fu Chong, Yun Ling Tan
  • Patent number: 10395987
    Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chia Ching Yeo, Kiok Boone Elgin Quek, Khee Yong Lim, Jae Han Cha, Yung Fu Chong
  • Publication number: 20190252515
    Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.
    Type: Application
    Filed: February 14, 2018
    Publication date: August 15, 2019
    Inventors: Hao Nong, Liang Li, Chiew Wah Yap, Ting Huo, Yung Fu Chong, Yun Ling Tan
  • Publication number: 20170200649
    Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 13, 2017
    Inventors: Chia Ching YEO, Kiok Boone Elgin QUEK, Khee Yong LIM, Jae Han CHA, Yung Fu CHONG
  • Patent number: 9390962
    Abstract: Methods for fabricating device substrates are provided where the device substrates have rounded trench corners in medium voltage (MV) and high voltage (HV) regions thereof to minimize interference with performance of MV or HV devices adjacent thereto. The fabricating methods involve thermally oxidizing a trench-forming area in an MV or HV region on a semiconductor substrate to form a silicon oxide layer having narrowed birds beak edges that create rounded trench shoulders semiconductor substrate. An isolation trench is then formed through the silicon oxide layer, into the semiconductor substrate, removing portion of the silicon oxide layer and leaving the birds beak edges. After removing the birds beak edges, an oxide layer is formed lining the trench and shoulders to create rounded trench corners in the MV or HV region. Trenches having rounded corners may be formed simultaneously with forming trenches in low voltage regions that don't have rounded trench corners.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lian Hoon Ko, Yung Fu Chong
  • Publication number: 20160172236
    Abstract: Integrated circuits and methods for fabricating device substrates and integrated circuits are provided. Integrated circuits in accordance with those described herein include a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region. The integrated circuits also have semiconductor devices thereon with isolation trenches in between them. The corners of the trenches in MV and HV regions of the integrated circuit are more rounded than the corners of the trenches in the LV region so that interference by trench corners in the MV and HV regions with the operation and performance of adjacent MV or HV device is minimized.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Lian Hoon Ko, Yung Fu Chong
  • Publication number: 20150008528
    Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Shyue Seng TAN, Lee Wee TEO, Yung Fu CHONG, Elgin QUEK, Sanford CHU
  • Patent number: 8912567
    Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: December 16, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Holt
  • Patent number: 8643119
    Abstract: A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: February 4, 2014
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTD
    Inventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
  • Patent number: 8450775
    Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 28, 2013
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Robert Holt
  • Patent number: 8324031
    Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Lee Wee Teo, Yung Fu Chong, Elgin Quek, Sanford Chu