Patents by Inventor Yung Fu Chong

Yung Fu Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566441
    Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Hao Nong, Liang Li, Chiew Wah Yap, Ting Huo, Yung Fu Chong, Yun Ling Tan
  • Patent number: 10395987
    Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chia Ching Yeo, Kiok Boone Elgin Quek, Khee Yong Lim, Jae Han Cha, Yung Fu Chong
  • Publication number: 20190252515
    Abstract: Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.
    Type: Application
    Filed: February 14, 2018
    Publication date: August 15, 2019
    Inventors: Hao Nong, Liang Li, Chiew Wah Yap, Ting Huo, Yung Fu Chong, Yun Ling Tan
  • Publication number: 20170200649
    Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 13, 2017
    Inventors: Chia Ching YEO, Kiok Boone Elgin QUEK, Khee Yong LIM, Jae Han CHA, Yung Fu CHONG
  • Patent number: 9390962
    Abstract: Methods for fabricating device substrates are provided where the device substrates have rounded trench corners in medium voltage (MV) and high voltage (HV) regions thereof to minimize interference with performance of MV or HV devices adjacent thereto. The fabricating methods involve thermally oxidizing a trench-forming area in an MV or HV region on a semiconductor substrate to form a silicon oxide layer having narrowed birds beak edges that create rounded trench shoulders semiconductor substrate. An isolation trench is then formed through the silicon oxide layer, into the semiconductor substrate, removing portion of the silicon oxide layer and leaving the birds beak edges. After removing the birds beak edges, an oxide layer is formed lining the trench and shoulders to create rounded trench corners in the MV or HV region. Trenches having rounded corners may be formed simultaneously with forming trenches in low voltage regions that don't have rounded trench corners.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lian Hoon Ko, Yung Fu Chong
  • Publication number: 20160172236
    Abstract: Integrated circuits and methods for fabricating device substrates and integrated circuits are provided. Integrated circuits in accordance with those described herein include a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region. The integrated circuits also have semiconductor devices thereon with isolation trenches in between them. The corners of the trenches in MV and HV regions of the integrated circuit are more rounded than the corners of the trenches in the LV region so that interference by trench corners in the MV and HV regions with the operation and performance of adjacent MV or HV device is minimized.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Lian Hoon Ko, Yung Fu Chong
  • Publication number: 20150008528
    Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Shyue Seng TAN, Lee Wee TEO, Yung Fu CHONG, Elgin QUEK, Sanford CHU
  • Patent number: 8912567
    Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: December 16, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Holt
  • Patent number: 8643119
    Abstract: A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: February 4, 2014
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing LTD
    Inventors: Zhijiong Luo, Huilong Zhu, Yung Fu Chong, Hung Y. Ng, Kern Rim, Nivo Rovedo
  • Patent number: 8450775
    Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 28, 2013
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Robert Holt
  • Patent number: 8324031
    Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Lee Wee Teo, Yung Fu Chong, Elgin Quek, Sanford Chu
  • Patent number: 8288825
    Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Judson Robert Holt
  • Patent number: 8211761
    Abstract: A semiconductor method includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the silicon-germanium layer. An interlevel dielectric layer is formed over the gate and the source/drain regions. A plurality of contacts is formed in the interlevel dielectric layer to the gate and the plurality of source/drain regions.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: July 3, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shyue Seng Tan, Yung Fu Chong, Lee Wee Teo
  • Patent number: 8138055
    Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: March 20, 2012
    Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann, Jingyu Lian, Yung Fu Chong
  • Publication number: 20120001228
    Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION (IBM), GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yung Fu CHONG, Zhijiong LUO, Judson Robert HOLT
  • Patent number: 8017487
    Abstract: A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: September 13, 2011
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Judson Robert Holt
  • Patent number: 7972921
    Abstract: A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, growing the substrate to surround the base insulator region, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: July 5, 2011
    Assignees: GlobalFoundries Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yung Fu Chong, Zhijiong Luo
  • Patent number: 7939413
    Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 10, 2011
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Brian Joseph Greene, Kern Rim
  • Patent number: 7892905
    Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: February 22, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Kuang Kian Ong, Kin Leong Pey, King Jien Chui, Ganesh Samudra, Yee Chia Yeo, Yung Fu Chong
  • Patent number: 7888224
    Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: February 15, 2011
    Assignees: Nanyang Technological University, Chartered Semiconductor Manufacturing Ltd., National University Of Singapore
    Inventors: Kuang Kian Ong, Sai Hooi Yeong, Kin Leong Pey, Lap Chan, Yung Fu Chong