Abstract: A reinforcement learning method for frame-level bit allocation is disclosed. The reinforcement learning method includes steps of: (a) at a testing time, computing a state according to a plurality of features; (b) determining an action according to a policy; (c) determining a number of bits allocated to an i-th frame in a group of pictures (GOP) according to the action, a GOP-level bit budget and the state, wherein i is a positive integer; (d) encoding the i-th frame according to the number of bits allocated to the i-th frame in the GOP; and (e) repeating the steps (a)˜(d) until an end of the GOP.

Abstract: A reinforcement learning method for frame-level bit allocation is disclosed. The reinforcement learning method includes steps of: (a) at a testing time, computing a state according to a plurality of features; (b) determining an action according to a policy; (c) determining a number of bits allocated to an i-th frame in a group of pictures (GOP) according to the action, a GOP-level bit budget and the state, wherein i is a positive integer; (d) encoding the i-th frame according to the number of bits allocated to the i-th frame in the GOP; and (e) repeating the steps (a)˜(d) until an end of the GOP.

Abstract: A memory device comprising a conglomerate material interposed between a first electrode and a second electrode is provided. The conglomerate material includes nanocrystalline grains embedded in an amorphous matrix. During operations, phase change reactions occur at the inter-grain boundaries in the conglomerate material so as to reduce the operation power.

Abstract: A memory device comprising a conglomerate material interposed between a first electrode and a second electrode is provided. The conglomerate material includes nanocrystalline grains embedded in an amorphous matrix. During operations, phase change reactions occur at the inter-grain boundaries in the conglomerate material so as to reduce the operation power.

Abstract: An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.