Patents by Inventor Yung-hsiang Lee

Yung-hsiang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8161092
    Abstract: System and method for processing symbols in a communication system are disclosed and may include in a processor that receives symbols to be coded for transmission over a wireless medium, grouping elements of an input matrix across a second dimension of the input matrix to form groups of matrix elements while multiplying the input matrix and an input vector. The input vector may include the symbols to be coded for transmission over the wireless medium. The method may also include pre-computing possible permutations of partial results for each of the groups of matrix elements, and assigning the partial results from each of the groups of matrix elements to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: April 17, 2012
    Assignee: Broadcom Corporation
    Inventor: Yung-Hsiang Lee
  • Patent number: 7472150
    Abstract: A method and system for time sharing N consecutive half-band decimating-by-2-filters using a single filter. Aspects of the method may comprise selecting a latched input signal and filtering, via a single decimating filter, the selected latched input signal to generate a first output signal. The method may also comprise latching the fed back portion of the first output signal. This latched signal may also be filtered by the single decimating filter to generate at least a second decimated output signal. A final output signal may be generated by latching at least one of the first output signal and the second decimated output signal. The final output signal may be latched utilizing at least one of a plurality of clocking signals.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: December 30, 2008
    Assignee: Broadcom Corporation
    Inventor: Sean (Yung-Hsiang) Lee
  • Publication number: 20080140752
    Abstract: System and method for processing symbols in a communication system are disclosed and may include in a processor that receives symbols to be coded for transmission over a wireless medium, grouping elements of an input matrix across a second dimension of the input matrix to form groups of matrix elements while multiplying the input matrix and an input vector. The input vector may include the symbols to be coded for transmission over the wireless medium. The method may also include pre-computing possible permutations of partial results for each of the groups of matrix elements, and assigning the partial results from each of the groups of matrix elements to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results.
    Type: Application
    Filed: January 21, 2008
    Publication date: June 12, 2008
    Inventor: Yung-hsiang Lee
  • Patent number: 7321915
    Abstract: A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of the input matrix to form groups of matrix elements. All possible permutations of partial results for each of the groups of matrix elements are pre-computed. The partial results from each of the groups of matrix elements are assigned to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results. The assigned partial results are summed along the first dimension of the matrix of assigned partial results to form a vector of full matrix multiplication results.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: January 22, 2008
    Assignee: Broadcom Corporation
    Inventor: Yung-hsiang Lee
  • Patent number: 7159154
    Abstract: A computer processor includes a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Yung-Hsiang Lee, Douglas M. Carmean, Rohit A. Vidwans
  • Patent number: 7139902
    Abstract: A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump instructions. Trace cache within a computer architecture is used to receive computer instructions at a first rate and to store the computer instructions as traces of instructions. An instruction execution pipeline is also provided to receive, decode, and execute the computer instructions at a second rate that is less than the first rate. A mux is also provided between the trace cache and the instruction execution pipeline to select a next instruction to be loaded into the instruction execution pipeline from the trace cache based, in part, on a branch result fed back to the mux from the instruction execution pipeline.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: November 21, 2006
    Assignee: Broadcom Corporation
    Inventor: Yung-hsiang Lee
  • Publication number: 20040153769
    Abstract: A computer processor includes a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.
    Type: Application
    Filed: July 8, 2003
    Publication date: August 5, 2004
    Inventors: Yung-Hsiang Lee, Douglas M. Carmean, Rohit A. Vidwans
  • Publication number: 20040083352
    Abstract: A method and apparatus are disclosed for enhancing the pipelined instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump instructions. Trace cache within a computer architecture is used to receive computer instructions at a first rate and to store the computer instructions as traces of instructions. An instruction execution pipeline is also provided to receive, decode, and execute the computer instructions at a second rate that is less than the first rate. A mux is also provided between the trace cache and the instruction execution pipeline to select a next instruction to be loaded into the instruction execution pipeline from the trace cache based, in part, on a branch result fed back to the mux from the instruction execution pipeline.
    Type: Application
    Filed: February 3, 2003
    Publication date: April 29, 2004
    Inventor: Yung-Hsiang Lee
  • Publication number: 20040083253
    Abstract: A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of the input matrix to form groups of matrix elements. All possible permutations of partial results for each of the groups of matrix elements are pre-computed. The partial results from each of the groups of matrix elements are assigned to each of a corresponding index of a first dimension of the input matrix to form a matrix of assigned partial results. The assigned partial results are summed along the first dimension of the matrix of assigned partial results to form a vector of full matrix multiplication results.
    Type: Application
    Filed: February 3, 2003
    Publication date: April 29, 2004
    Inventor: Yung-Hsiang Lee
  • Patent number: 6629271
    Abstract: A computer processor includes a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: September 30, 2003
    Assignee: Intel Corporation
    Inventors: Yung-Hsiang Lee, Douglas M. Carmean, Rohit A. Vidwans
  • Patent number: 4741059
    Abstract: A combined tool unit constructed so as to be disassembled and reorganized into various independent tools. The tool unit includes a cylindrical hammer portion which can be received between a pair of hand grips of a tongs portion in the storage position of the tool unit. The hammer portion can be fixedly mounted on the closed jaws of the tongs portion to form an independent hammer. A saw blade can be removed from one of the hand grips of the tongs portion and locked into one end of the hammer portion to form an independent saw. A screwdriver bit can be removed from another end of the hammer portion and locked into the same end of the hammer portion where the saw blade can be locked, to form an independent screwdriver. The tongs when disassembled from the hammer portion can be used as a conventional pair of pincers.
    Type: Grant
    Filed: March 9, 1987
    Date of Patent: May 3, 1988
    Assignee: Yau-Zung Pan
    Inventors: Yung-Hsiang Lee, Yau-Zung Pan