Abstract: A semiconductor device may include a plate layer, gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer, extending to different lengths in a second direction perpendicular to the first direction and forming step regions, channel structures penetrating through the gate electrodes, extending in the first direction, and each including a channel layer, isolation regions penetrating through the gate electrodes and extending in the first direction and the second direction, sacrificial insulating layers on the same levels as levels of the gate electrodes, respectively, a through-via penetrating through the sacrificial insulating layers and extending in the first direction, a dam structure surrounding the through-via, and a guard structure spaced apart from the dam structure horizontally and having a closed loop shape surrounding the dam structure on a plan view.

Abstract: Aspects of a storage device are provided for handling detection and operations associated with an erase block type of the block. The storage device includes one or more non-volatile memories each including a block, and one or more controllers operable to cause the storage device to perform erase type detection and associated operations for single blocks or metablocks. For instance, the controller(s) may erase the block prior to a power loss event, perform at least one read of the block following the power loss event, identify the erase block type of the block in response to the at least one read, and program the block based on the identified erase block type without performing a subsequent erase prior to the program. The controller(s) may also perform metablock operations associated with the identified erase block type. Thus, unnecessary erase operations during recovery from an ungraceful shutdown (UGSD) may be mitigated.

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a source structure that includes a support source layer, a gate stack structure on the support source layer, a memory channel structure that penetrates through the gate stack structure and the support source layer, and a separation structure that penetrates through the gate stack structure and the support source layer. The support source layer includes a first source part through which the memory channel structure penetrates, and a second source part through which the separation structure penetrates. A top surface of the first source part is at a level lower than that of a top surface of the second source part.

Abstract: Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.

Abstract: Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.