Patents by Inventor Yuri Granik
Yuri Granik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11061373Abstract: A method and system for calculating probability of success or failure for a lithographic process due to stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, such as photon shot noise and stochastic phenomena in the resist process and resist development, with the resulting stochastic randomness potentially becoming a major challenge. The stochastic phenomena are modeled using a stochastic model, such as a random field model, that models stochastic randomness the exposure and resist process. The stochastic model inputs light exposure and resist parameters and definitions of success of success or failure as to the lithographic process, and outputs a probability distribution function of deprotection concentration indicative of success or failure probability of the lithographic process.Type: GrantFiled: August 20, 2019Date of Patent: July 13, 2021Assignee: Siemens Industry Software Inc.Inventors: Gurdaman Khaira, Germain Louis Fenger, Azat Latypov, John L. Sturtevant, Yuri Granik
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Patent number: 10248028Abstract: A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, pixel solutions are constrained from solutions that are bright, continuous, and smooth. In another embodiment, the light source optimization and resolution enhancement technique(s) are iteratively performed to minimize errors in a printed pattern of features.Type: GrantFiled: April 21, 2016Date of Patent: April 2, 2019Assignee: Mentor Graphics CorporationInventor: Yuri Granik
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Patent number: 9678435Abstract: Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local minimal light intensity values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local minimal light intensity values represents a minimum light intensity value for an area surrounding one of the plurality of sample points. Based on the local minimal light intensity values, horizontal development bias values for the plurality of sample points are then determined. Finally, resist contour data of the feature are determined based at least on the horizontal development bias values.Type: GrantFiled: September 22, 2014Date of Patent: June 13, 2017Assignee: Mentor Graphics, A Siemens BusinessInventors: Yunfei Deng, Yuri Granik, Dmitry Medvedev, Yuan He, Konstantinos Adam
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Publication number: 20160238950Abstract: A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, pixel solutions are constrained from solutions that are bright, continuous, and smooth. In another embodiment, the light source optimization and resolution enhancement technique(s) are iteratively performed to minimize errors in a printed pattern of features.Type: ApplicationFiled: April 21, 2016Publication date: August 18, 2016Applicant: Mentor Graphics CorporationInventor: Yuri Granik
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Patent number: 9418195Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.Type: GrantFiled: September 8, 2014Date of Patent: August 16, 2016Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
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Patent number: 9355201Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.Type: GrantFiled: August 19, 2013Date of Patent: May 31, 2016Assignee: Mentor Graphics CorporationInventor: Yuri Granik
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Publication number: 20160140278Abstract: Aspects of the disclosed techniques relate to techniques for resist simulation in lithography. Local light power values are determined for a plurality of sample points in boundary regions of an aerial image of a feature to be printed on a resist coating, wherein each of the local light power values represents a light power value for an area surrounding one of the plurality of sample points. Based on the local light power values, a vertical shrinkage function is constructed. Resist contour data of the feature are then computed based at least on resist shrinkage effects modeled using the local light power values and the vertical shrinkage function.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Yunfei Deng, Yuri Granik, Dmitry Medvedev, Konstantinos Adam
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Patent number: 9330228Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.Type: GrantFiled: April 22, 2015Date of Patent: May 3, 2016Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Joydeep Mitra, Yuansheng Ma, Krasnova Polina Andreevna, Yuri Granik
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Patent number: 9323161Abstract: A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, a method includes selecting a pattern of layout features by determining one or more periodic patterns of features that occurs in the layout database, defining a mathematical relationship between pixel intensities produced by a diffractive optical element and the selected pattern of features, where the mathematical relationship includes a heavier weighting for the periodic patterns of features, and assigning pixel intensities for the diffractive optical element using the mathematical relationship, where the pixel intensities are calculated to print the periodic features with greater image fidelity in proportion to the heavier weighting.Type: GrantFiled: October 26, 2009Date of Patent: April 26, 2016Assignee: Mentor Graphics CorporationInventor: Yuri Granik
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Publication number: 20150227676Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: Juan Andres Torres Robles, Joydeep Mitra, Yuansheng Ma, Krasnova Polina Andreevna, Yuri Granik
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Publication number: 20150143323Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Juan Andres Torres Robles, Yuri Granik, Kyohei Sakajiri
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Patent number: 9032357Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.Type: GrantFiled: November 18, 2013Date of Patent: May 12, 2015Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Yuri Granik, Kyohei Sakajiri
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Patent number: 9009643Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.Type: GrantFiled: August 19, 2013Date of Patent: April 14, 2015Assignee: Mentor Graphics CorporationInventor: Yuri Granik
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Publication number: 20150067628Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.Type: ApplicationFiled: September 8, 2014Publication date: March 5, 2015Inventors: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
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Patent number: 8843859Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.Type: GrantFiled: October 11, 2012Date of Patent: September 23, 2014Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
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Publication number: 20140229903Abstract: Aspects of the invention relate to techniques of optical simulation for topographically non-uniform substrates. A layout design is simulated to generate an aerial image based on optical models for different types of substrates and for transition regions, along with models for one or more categories of light signals. The one or more categories of light signals comprise trench side-wall reflection signals, trench radiation signals, and trench corner diffraction signals. The one or more categories of light signals may further comprise gate scattering signals and interconnect scattering signals. The models for the one or more categories of light signals may be calibrated with experimental data.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventors: Yuri Granik, Uwe Hollerbach, Konstantinos Adam
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Patent number: 8799832Abstract: Aspects of the invention relate to techniques of optical simulation for topographically non-uniform substrates. A layout design is simulated to generate an aerial image based on optical models for different types of substrates and for transition regions, along with models for one or more categories of light signals. The one or more categories of light signals comprise trench side-wall reflection signals, trench radiation signals, and trench corner diffraction signals. The one or more categories of light signals may further comprise gate scattering signals and interconnect scattering signals. The models for the one or more categories of light signals may be calibrated with experimental data.Type: GrantFiled: February 8, 2013Date of Patent: August 5, 2014Assignee: Mentor Graphics CorporationInventors: Yuri Granik, Uwe Hollerbach, Konstantinos Adam
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Patent number: 8788982Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, transition and visible portions. An inverse lithography process is then performed on the core and transition portions of the re-correction region while taking into account effects from the visible portion to generate a modified re-correction region. The transition portion is processed based on distance from boundary between the transition portion and the core portion such that layout features near the boundary between the transition portion and the core portion are adjusted more than layout features farther away from the boundary.Type: GrantFiled: January 14, 2013Date of Patent: July 22, 2014Assignee: Mentor Graphics CorporationInventors: George Lippincott, Yuri Granik, Sergey Kobelkov
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Publication number: 20140053123Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.Type: ApplicationFiled: August 19, 2013Publication date: February 20, 2014Applicant: Mentor Graphics CorporationInventor: Yuri Granik
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Patent number: 8607168Abstract: Techniques for model calibration and alignment of measurement contours of printed layout features with simulation contours obtained with a model are disclosed. With various implementations of the invention, contour point errors are determined. Based on the contour point errors and a cost function, values of alignment parameters may be determined. The values of alignment parameters may be used to realign the measurement contours for model calibration. The alignment may be conducted concurrently with model calibration.Type: GrantFiled: April 22, 2011Date of Patent: December 10, 2013Assignee: Mentor Graphics CorporationInventors: Ir Kusnadi, Thuy Q Do, Yuri Granik, John L Sturtevant