Patents by Inventor Yushi Koyama

Yushi Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220014837
    Abstract: A length of a band part is easily adjusted with the same length regardless of the number of adjustments. There are provided an information output unit configured to output information, a band part whose length is adjustable, and a slide part that is movable with respect to the band part in a length direction of the band part. The slide part is attached with a holding magnet, the band part supports a positioning magnet configured to attract the holding magnet in a state where the length of the band part is adjusted, and the positioning magnet is made movable with respect to the band part in a length direction.
    Type: Application
    Filed: October 15, 2019
    Publication date: January 13, 2022
    Inventors: KOHEI KIKUCHI, YUSHI KOYAMA
  • Patent number: 10938319
    Abstract: According to an embodiment, there is provided an apparatus which can hold down an energy loss and can avoid an increase in size. The apparatus includes a cell including a floating capacitor connected in parallel to an upper-side switching element and a lower-side switching element; an upper arm include including first switch circuits, each including a first switching element, a first diode and a first capacitor, are connected in series; a lower arm including second switch circuits, each including a second switching element, a second diode and a second capacitor, are connected in series; and a circuit which connects a low-side terminal of the cell and a low-side terminal of the first capacitor and connects a high-side terminal of the cell and a high-side terminal of the second capacitor.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 2, 2021
    Assignee: Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Koji Maki, Hiroshi Mochikawa, Yushi Koyama, Shunsuke Tamada, Takuro Arai, Ryuichi Morikawa, Mami Mizutani
  • Patent number: 10932029
    Abstract: Provided is a headphone that includes a housing that houses a sound output unit, a slider configured to support the housing, and a support unit attached to a head mounted display. The support unit slidably supports the slider and the support unit is attached to a band of the head mounted display.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 23, 2021
    Assignee: SONY CORPORATION
    Inventors: Tomohiro Ito, Yushi Koyama
  • Publication number: 20200350832
    Abstract: According to an embodiment, there is provided an apparatus which can hold down an energy loss and can avoid an increase in size. The apparatus includes a cell including a floating capacitor connected in parallel to an upper-side switching element and a lower-side switching element; an upper arm include including first switch circuits, each including a first switching element, a first diode and a first capacitor, are connected in series; a lower arm including second switch circuits, each including a second switching element, a second diode and a second capacitor, are connected in series; and a circuit which connects a low-side terminal of the cell and a low-side terminal of the first capacitor and connects a high-side terminal of the cell and a high-side terminal of the second capacitor.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Applicant: Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Koji MAKI, Hiroshi Mochikawa, Yushi Koyama, Shunsuke Tamada, Takuro Arai, Ryuichi Morikawa, Mami Mizutani
  • Publication number: 20190394555
    Abstract: A headphone includes: a housing that houses a sound output unit; a slider configured to support the housing; and a support unit attached to a head mounted display and configured to slidably support the slider.
    Type: Application
    Filed: February 28, 2018
    Publication date: December 26, 2019
    Inventors: TOMOHIRO ITO, YUSHI KOYAMA
  • Patent number: 9893509
    Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: February 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Mochikawa, Atsuhiko Kuzumaki, Junichi Tsuda, Yushi Koyama
  • Patent number: 9379548
    Abstract: A reactive power compensator according to an embodiment comprises: multilevel inverter circuits respectively constituting each of the three phases; a filter circuit for reducing harmonics connected between the output terminals of each of the multilevel inverter circuits and a power system interconnection terminal; and a control section for causing prescribed three-phase AC voltage to be output by controlling each of said multilevel inverter circuits. Each of the multilevel inverter circuits is constituted by connecting in series one or more single-phase full-bridge single-pulse inverters and is arranged to convert DC voltage to respective positive and negative single-pulse voltages once per cycle of the fundamental wave of the voltage instruction value.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yushi Koyama, Yosuke Nakazawa, Hiroshi Mochikawa, Atsuhiko Kuzumaki, Takeru Murao
  • Publication number: 20160134098
    Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi MOCHIKAWA, Atsuhiko KUZUMAKI, Junichi TSUDA, Yushi KOYAMA
  • Patent number: 9257248
    Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: February 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Mochikawa, Atsuhiko Kuzumaki, Junichi Tsuda, Yushi Koyama
  • Publication number: 20140133198
    Abstract: A reactive power compensator according to an embodiment comprises: multilevel inverter circuits respectively constituting each of the three phases; a filter circuit for reducing harmonics connected between the output terminals of each of the multilevel inverter circuits and a power system interconnection terminal; and a control section for causing prescribed three-phase AC voltage to be output by controlling each of said multilevel inverter circuits. Each of the multilevel inverter circuits is constituted by connecting in series one or more single-phase full-bridge single-pulse inverters and is arranged to convert DC voltage to respective positive and negative single-pulse voltages once per cycle of the fundamental wave of the voltage instruction value.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Inventors: Yushi Koyama, Yosuke Nakazawa, Hiroshi Mochikawa, Atsuhiko Kuzumaki, Takeru Murao
  • Patent number: 8514596
    Abstract: The present invention includes: an inverter 1 configured to perform pulse wide modulation on an output from a DC power source 5; a first capacitor pair 41 provided at an input side of the inverter and including two capacitors serially connected to form a neutral point; a second capacitor pair 42 provided at an output side of the inverter and including two capacitors serially connected to form a neutral point; a bypass path g for a leakage current formed by connecting the neutral point of the first capacitor pair and the neutral point of the second capacitor pair to each other; at least one common mode choke coil 3 provided between the first capacitor pair and the second capacitor pair and configured to suppress a common mode current generated in the inverter; and an output filter 2 configured to convert a voltage, which is outputted from the inverter and subjected to the pulse wide modulation, into a voltage in a sine wave form.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yushi Koyama, Junichi Tsuda, Hiroshi Mochikawa
  • Patent number: 8472215
    Abstract: According to one embodiment, a grid-tie inverter includes: a inverter performing pulse width modulation for a DC voltage; a first capacitor circuit connected to an input side of the inverter so as to form a neutral point; a second capacitor circuit connected to an output side of the inverter so as to form a neutral point; a common mode current bypass channel formed by connecting the neutral points of the first capacitor circuit and the second capacitor circuit; a grounded capacitor provided between the bypass channel and a ground; a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit; and an output filter converting a pulse width-modulated voltage outputted from the inverter into a sine AC voltage.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: June 25, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yushi Koyama, Junichi Tsuda, Hiroshi Mochikawa
  • Publication number: 20130134958
    Abstract: According to one embodiment, a switch includes a first element with a first withstand voltage, a second element whose withstand voltage is lower than the first withstand voltage, a diode which is connected between a positive electrode of the first element and a positive electrode of the second element in such a manner that a direction from the positive electrode of the second element toward the positive electrode of the first element is a forward direction and whose withstand voltage is equal to the first withstand voltage, a negative electrode of the first element and a negative electrode of the second element being connected, and a circuit configured to apply a positive voltage to the positive terminal output a pulse lower than the first withstand voltage when the first element goes off.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 30, 2013
    Inventors: Hiroshi MOCHIKAWA, Atsuhiko KUZUMAKI, Junichi TSUDA, Yushi KOYAMA
  • Publication number: 20120275201
    Abstract: According to one embodiment, a grid-tie inverter includes: a inverter performing pulse width modulation for a DC voltage; a first capacitor circuit connected to an input side of the inverter so as to form a neutral point; a second capacitor circuit connected to an output side of the inverter so as to form a neutral point; a common mode current bypass channel formed by connecting the neutral points of the first capacitor circuit and the second capacitor circuit; a grounded capacitor provided between the bypass channel and a ground; a first common mode choke coil unit including a common mode choke coil at least one of between the first capacitor circuit and the inverter and between the inverter and the second capacitor circuit; and an output filter converting a pulse width-modulated voltage outputted from the inverter into a sine AC voltage.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Inventors: Yushi KOYAMA, Junichi TSUDA, Hiroshi MOCHIKAWA
  • Publication number: 20110216568
    Abstract: The present invention includes: an inverter 1 configured to perform pulse wide modulation on an output from a DC power source 5; a first capacitor pair 41 provided at an input side of the inverter and including two capacitors serially connected to form a neutral point; a second capacitor pair 42 provided at an output side of the inverter and including two capacitors serially connected to form a neutral point; a bypass path g for a leakage current formed by connecting the neutral point of the first capacitor pair and the neutral point of the second capacitor pair to each other; at least one common mode choke coil 3 provided between the first capacitor pair and the second capacitor pair and configured to suppress a common mode current generated in the inverter; and an output filter 2 configured to convert a voltage, which is outputted from the inverter and subjected to the pulse wide modulation, into a voltage in a sine wave form.
    Type: Application
    Filed: July 21, 2009
    Publication date: September 8, 2011
    Inventors: Yushi Koyama, Junichi Tsuda, Hiroshi Mochikawa