Abstract: A semiconductor device includes: a chip including a main surface; a first conductivity type first semiconductor region formed at least in a surface layer portion of the main surface; a trench structure including a trench formed in the main surface to be located within the first semiconductor region, and a second conductivity type polysilicon mechanically and electrically connected to the chip and located within the trench; and a second conductivity type second semiconductor region formed within the first semiconductor region along a wall surface of the trench structure and forming a pn junction, as a photodiode, with the first semiconductor region.

Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.

Abstract: A semiconductor device, includes: a semiconductor substrate having first and second main surfaces; and first and second polysilicon layers doped with impurity, wherein the semiconductor substrate includes a diffusion layer doped with impurity, the diffusion layer is located between the first main surface and the second main surface, first and second grooves are formed on the first main surface in spaced-apart relationship along a first direction in a plan view, the first and second grooves each extend along a second direction orthogonal to the first direction in a plan view and extend toward the second main surface to reach the diffusion layer in a cross-sectional view orthogonal to the second direction, the first and second polysilicon layers are embedded in the first and second grooves, respectively, and lower ends of the first and second polysilicon layers are electrically connected to each other by the diffusion layer.

Abstract: A semiconductor device includes a semiconductor layer including a first main surface, a first region of a first conduction type that is formed at a surface layer portion of the first main surface, a second region of a first conduction type that is formed at the surface layer portion of the first main surface and is separated from the first region in a first direction, a channel region of a second conduction type that is formed between the first region and the second region in the surface layer portion of the first main surface, a first gate electrode that is formed in a vicinity of the first region in the first main surface, faces the channel region, and includes a first side portion and a second side portion on an opposite side of the first side portion in the first direction.

Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.

Abstract: A semiconductor device of the present invention includes a first interlayer film having a first region and a second region, a MIM structure including a lower electrode formed on the second region, a first capacitance film formed on the lower electrode, and an upper electrode formed on the first capacitance film, a lower metal layer formed on the first region, and disposed in the same layer level with the lower electrode, an auxiliary metal layer disposed in the same layer level with the upper electrode, and opposed to the lower metal layer, a second interlayer film formed on the first interlayer film, and covering the auxiliary metal layer and the MIM structure, and a top metal layer formed on the second interlayer film, and penetrating through the second interlayer film to contact the auxiliary metal layer.

Abstract: A semiconductor device of the present invention includes a first interlayer film having a first region and a second region, a MIM structure including a lower electrode formed on the second region, a first capacitance film formed on the lower electrode, and an upper electrode formed on the first capacitance film, a lower metal layer formed on the first region, and disposed in the same layer level with the lower electrode, an auxiliary metal layer disposed in the same layer level with the upper electrode, and opposed to the lower metal layer, a second interlayer film formed on the first interlayer film, and covering the auxiliary metal layer and the MIM structure, and a top metal layer formed on the second interlayer film, and penetrating through the second interlayer film to contact the auxiliary metal layer.

Abstract: A semiconductor device includes a high breakdown voltage DMOS transistor formed on a first conductivity type semiconductor substrate. The semiconductor device includes: a DMOS second conductivity type well; a DMOS first conductivity body region; a DMOS second conductivity type source region; a DMOS second conductivity type drain region; a LOCOS oxide film formed between the DMOS second conductivity type drain region and the DMOS first conductivity type body region; and a DMOS gate insulating film formed in succession to the LOCOS oxide film to cover a DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well, wherein the DMOS gate insulating film includes a first insulating film which is disposed outside the DMOS channel region and a second insulating film which is disposed in the DMOS channel region and is thinner than the first insulating film.

Abstract: An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window.

Abstract: A semiconductor device includes a high breakdown voltage DMOS transistor formed on a first conductivity type semiconductor substrate. The semiconductor device includes: a DMOS second conductivity type well; a DMOS first conductivity body region; a DMOS second conductivity type source region; a DMOS second conductivity type drain region; a LOCOS oxide film formed between the DMOS second conductivity type drain region and the DMOS first conductivity type body region; and a DMOS gate insulating film formed in succession to the LOCOS oxide film to cover a DMOS channel region between the DMOS second conductivity type source region and the DMOS second conductivity type well, wherein the DMOS gate insulating film includes a first insulating film which is disposed outside the DMOS channel region and a second insulating film which is disposed in the DMOS channel region and is thinner than the first insulating film.

Abstract: An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window.

Abstract: A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region 25 as an impurity region formed under a tunnel window 12 and a channel stopper region 19 formed under a LOCOS oxide film 18 are spaced apart by a predetermined distance Y. Therefore, the tunnel window 12 does not sustain damage if an excessive voltage is applied to the tunnel window 12. As a result, the FLOTOX-TYPE EEPROM is adapted to limit the voltage applied to the tunnel window 12 and to reduce stress on the tunnel window 12 and can achieve an increased number of rewrites.

Abstract: A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window; a plurality of select gates 13 provided in one-on-one correspondence to the plural floating gates 11; a control gate 16 shared by the plural floating gates 11; a source 17 shared by the plural floating gates 11; and a drain 18 shared by the plural floating gates 11. Therefore, the FLOTOX EEPROM does not encounter the decrease of junction breakdown voltage of a drain region, allowing the application of sufficiently high write voltage. Further, cell area can be reduced.

Abstract: In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates (25a, 25b), two tunnel windows (33a, 33b) a shared source (27), a shared control gate (26), select gates (29a, 29b), and a shared drain 28. Thus, a higher reliability design and a higher breakdown voltage design are achieved for the FLOTOX EEPROM of the dual cell type.

Abstract: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate.

Abstract: A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window; a plurality of select gates 13 provided in one-on-one correspondence to the plural floating gates 11; a control gate 16 shared by the plural floating gates 11; a source 17 shared by the plural floating gates 11; and a drain 18 shared by the plural floating gates 11. Therefore, the FLOTOX EEPROM does not encounter the decrease of junction breakdown voltage of a drain region, allowing the application of sufficiently high write voltage. Further, cell area can be reduced.

Abstract: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate.

Abstract: A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region 25 as an impurity region formed under a tunnel window 12 and a channel stopper region 19 formed under a LOCOS oxide film 18 are spaced apart by a predetermined distance Y. Therefore, the tunnel window 12 does not sustain damage if an excessive voltage is applied to the tunnel window 12. As a result, the FLOTOX-TYPE EEPROM is adapted to limit the voltage applied to the tunnel window 12 and to reduce stress on the tunnel window 12 and can achieve an increased number of rewrites.

Abstract: In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates (25a, 25b), two tunnel windows (33a, 33b) a shared source (27), a shared control gate (26), select gates (29a, 29b), and a shared drain 28. Thus, a higher reliability design and a higher breakdown voltage design are achieved for the FLOTOX EEPROM of the dual cell type.

Abstract: A photoelectric conversion device includes a photoelectric conversion layer that is stacked on a semiconductor substrate and that has first, second, and third photoelectric conversion regions, and first, second, and third dividing regions. The first dividing region is formed at a predetermined depth from a surface of the photoelectric conversion layer in the first photoelectric conversion region, and divides the first photoelectric conversion region into a first surface side region closer to the surface thereof and a first substrate side region closer to the semiconductor substrate. The first dividing region has a through hole. The second dividing region is formed at substantially the same depth as the first dividing region or at a shallower depth than the first dividing region in the second photoelectric conversion region. The third dividing region is formed at a shallower depth than the second dividing region in the third photoelectric conversion region.