Patents by Inventor Yusuf A. Haque

Yusuf A. Haque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180154394
    Abstract: An imaging device includes a two dimensional array of piezoelectric elements. Each piezoelectric element includes: a piezoelectric layer; a bottom electrode disposed on a bottom side of the piezoelectric layer and configured to receive a transmit signal during a transmit mode and develop an electrical charge during a receive mode; and a first top electrode disposed on a top side of the piezoelectric layer; and a first conductor, wherein the first top electrodes of a portion of the piezoelectric elements in a first column of the two dimensional array are electrically coupled to the first conductor.
    Type: Application
    Filed: November 29, 2017
    Publication date: June 7, 2018
    Applicant: EXO IMAGING INC.
    Inventors: Yusuf Haque, Sandeep Akkaraju, Janusz Bryzek
  • Publication number: 20180153510
    Abstract: A transceiver includes an array of pMUT elements, where each pMUT element includes: a substrate; a membrane suspending from the substrate; a bottom electrode disposed on the membrane; a piezoelectric layer disposed on the bottom electrode; and a first electrode disposed on the piezoelectric layer. Each pMUT element exhibits one or more modes of vibration.
    Type: Application
    Filed: November 29, 2017
    Publication date: June 7, 2018
    Applicant: EXO IMAGING INC.
    Inventors: Yusuf Haque, Sandeep Akkaraju, Janusz Bryzek
  • Publication number: 20180153512
    Abstract: An imaging system includes: a transceiver cell for generating a pressure wave and converting an external pressure wave into an electrical signal; and a control unit for controlling an operation of the transceiver cell. The transceiver cell includes: a substrate; at least one membrane suspending from the substrate; and a plurality of transducer elements mounted on the at least one membrane. Each of the plurality of transducer elements has a bottom electrode, a piezoelectric layer on bottom electrode, and at least one top electrode on the piezoelectric layer. Each of the plurality of transducer element generates a bending moment in response to applying an electrical potential across the bottom electrode and the at least one top electrode and develops an electrical charge in response to a bending moment due to the external pressure wave.
    Type: Application
    Filed: November 21, 2017
    Publication date: June 7, 2018
    Applicant: EXO IMAGING INC.
    Inventors: Sandeep Akkaraju, Haesung Kwon, Yusuf Haque, Janusz Bryzek
  • Patent number: 9071270
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 30, 2015
    Assignee: CREST SEMICONDUCTORS, INC.
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Patent number: 8890729
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: January 26, 2013
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Patent number: 8890739
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Publication number: 20140152478
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: January 26, 2013
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152477
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Publication number: 20130265182
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Patent number: 8542143
    Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: September 24, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
  • Publication number: 20130234870
    Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
  • Patent number: 8525556
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Patent number: 8525596
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8497790
    Abstract: A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 30, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Paul Talmage Watkins, Rex K. Hales, Yusuf Haque
  • Patent number: 8466818
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: June 18, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Publication number: 20130141261
    Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
  • Publication number: 20130120066
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8344722
    Abstract: A method for measuring electric current applied to a load includes: with a sensor element having an inaccuracy, measuring an electric current supplied to a load to produce a measurement of the electric current; with the sensor element, measuring the electric current with an added perturbation current; and using measurements of the electric current taken with and without the perturbation current to refine the measurement of the electric current.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: January 1, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Marcellus C. Harper, William Picken, Yusuf Haque
  • Publication number: 20120194223
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: SIFLARE, INC.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Publication number: 20110279133
    Abstract: A method for measuring electric current applied to a load includes: with a sensor element having an inaccuracy, measuring an electric current supplied to a load to produce a measurement of the electric current; with the sensor element, measuring the electric current with an added perturbation current; and using measurements of the electric current taken with and without the perturbation current to refine the measurement of the electric current.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 17, 2011
    Applicant: SIFLARE, INC
    Inventors: Marcellus C. Harper, William Picken, Yusuf Haque