Patents by Inventor Yusuf A. Haque

Yusuf A. Haque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110279133
    Abstract: A method for measuring electric current applied to a load includes: with a sensor element having an inaccuracy, measuring an electric current supplied to a load to produce a measurement of the electric current; with the sensor element, measuring the electric current with an added perturbation current; and using measurements of the electric current taken with and without the perturbation current to refine the measurement of the electric current.
    Type: Application
    Filed: May 17, 2010
    Publication date: November 17, 2011
    Applicant: SIFLARE, INC
    Inventors: Marcellus C. Harper, William Picken, Yusuf Haque
  • Patent number: 8026838
    Abstract: A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: September 27, 2011
    Assignee: Siflare, Inc.
    Inventors: Rex K. Hales, Marcellus C. Harper, Tracy Johancsik, Yusuf Haque
  • Publication number: 20100321227
    Abstract: A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Applicant: SIFLARE INC.
    Inventors: Rex K. Hales, Marcellus C. Harper, Tracy Johancsik, Yusuf Haque
  • Patent number: 7068788
    Abstract: The present invention is related to digital to analog converter (DAC) input data encryption off-chip and decryption on-chip to suppress input data in-band harmonic leakage through package related parasitic capacitance. More specifically, the present invention relates to the method and apparatus of input data encryption off-chip by forming the logical exclusive-OR of the raw data and a random single bit data stream. The encrypted data is then read onto the DAC chip where the data is decrypted using identical circuitry and an identical random single bit data stream. The off-chip encryption isolates harmonic content within the input data, preventing leakage of input data harmonic content through IC package-related parasitic capacitance into DAC outputs. Any leakage appears as an increase in spectral noise rather than output distortion and as such, has a much smaller impact on DAC narrow band linearity.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: June 27, 2006
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yusuf A. Haque, Benjamin J. McCarroll, Kevin K. Johnstone
  • Publication number: 20020126839
    Abstract: The present invention is related to digital to analog converter (DAC) input data encryption off-chip and decryption on-chip to suppress input data in-band harmonic leakage through package related parasitic capacitance. More specifically, the present invention relates to the method and apparatus of input data encryption off-chip by forming the logical exclusive-OR of the raw data and a random single bit data stream. The encrypted data is then read onto the DAC chip where the data is decrypted using identical circuitry and an identical random single bit data stream. The off-chip encryption isolates harmonic content within the input data, preventing leakage of input data harmonic content through IC package-related parasitic capacitance into DAC outputs. Any leakage appears as an increase in spectral noise rather than output distortion and as such, has a much smaller impact on DAC narrow band linearity.
    Type: Application
    Filed: September 10, 2001
    Publication date: September 12, 2002
    Inventors: Yusuf A. Haque, Benjamin J. McCarroll, Kevin K. Johnstone
  • Patent number: 6407770
    Abstract: A technique is described for detecting defects such as short circuits in a device such as a discrete pixel detector used in a digital x-ray system. The technique employs test circuits associated with each row driver of the detector. The test circuits are enabled by a test enable signal, and the row driver sequentially enables the rows of the detector, along with the individual test circuits. In a test sequence, output signals from the row test circuits are monitored to identify whether a defect, such as a short circuit, is likely to exist in the row or row driver. The test circuitry adds only minimal area and complexity to the row driver function, providing a high degree of test coverage at a low cost, with minimal likelihood of test circuitry-induced failures.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: June 18, 2002
    Assignee: General Electric Company
    Inventors: Scott A. Bielski, Lawrence R. Skrenes, Yusuf A. Haque
  • Patent number: 6356225
    Abstract: An integrated circuit may include matched cells each having an active transconductor, wherein the matched cells are coupled together through respective active transconductor circuits to average the effect of comparator input-referred offsets. Each cell of the matched cells may have a first differential gain stage coupled to a second differential gain stage that is coupled to an output buffer stage, and an associated active transconductor circuit. The active transconductor of each cell is coupled to the gain stage of other cells to average the effect of cell mismatches.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: March 12, 2002
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kevin K. Johnstone, Yusuf A. Haque, Mark Albert Pinchback
  • Patent number: 5869986
    Abstract: A power level sense circuit which is substantially immune to variations in integrated circuit processing and operating temperature. The sense circuit uses a diode biased to a predetermined average conduction level as the primary element in an envelope detector to detect the envelope of the RF transmit signal. While the DC offset of the diode will vary with temperature and integrated circuit processing, the DC offset is eliminated by an auto zeroing procedure before each power sensing cycle.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: February 9, 1999
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yusuf A. Haque, Patrick Chan
  • Patent number: 5748010
    Abstract: A logic signal level translation method and apparatus having very low dropout with respect to the powering rails and having a tri-state mode of operation allowing the output terminal to be driven to voltages beyond the highest supply voltage coupled thereto without significant power dissipation within the circuit. The output circuit includes well or body snatching devices which are controlled to assure that the wells of the output devices are able to follow extremes in voltage of the output terminal without biasing to conduction a PN junction of one or more of the output devices. A preferred embodiment is disclosed.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: May 5, 1998
    Assignee: Maxim Integrated Products
    Inventor: Yusuf A. Haque
  • Patent number: 4801888
    Abstract: The invention relates to a self-biasing, programmable, universal active filter having an input section which includes an operational amplifier. The amplifier has one output and two input terminals. A first capacitor has one of its terminals coupled to a first of the input terminals of the amplifier and the other terminal serving as an input node to the filter. The second capacitor is coupled between the same input terminal and the output terminal. The filter has a bandpass section having an output and an input coupled to the output terminal of the amplifier. The filter has a low pass section having an output and an input coupled to the output of the bandpass section. The filter has a third capacitor coupled between the first input terminal of the amplifier and the output of the bandpass section.
    Type: Grant
    Filed: February 29, 1988
    Date of Patent: January 31, 1989
    Assignee: Maxim Integrated Products
    Inventor: Yusuf A. Haque
  • Patent number: 4596954
    Abstract: A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.
    Type: Grant
    Filed: February 29, 1984
    Date of Patent: June 24, 1986
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque
  • Patent number: 4590440
    Abstract: A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop.
    Type: Grant
    Filed: July 6, 1984
    Date of Patent: May 20, 1986
    Assignee: American Microsystems, Inc.
    Inventors: Yusuf A. Haque, Ashraf K. Takla
  • Patent number: 4580065
    Abstract: A single-shot circuit is fabricated as an integrated circuit except for a single capacitor requiring a single pin to connect to the on-chip circuitry. The single-shot is rendered independent of process variations and operating conditions by incorporating an analog feedback loop. The output of the single shot is detected by an analog circuit which includes a positive and negative voltage generator the ratio of whose voltages is a function of the desired duty cycle. The generators are actuated, respectively, when a pulse exists and when there is no pulse. The analog feedback circuit also includes an integrator for receiving and integrating the positive and negative voltages from the generators. The integrated and amplified voltages are fed back to the last stage of the single-shot circuit. When the duty cycle is high, the voltage that is fed back drives the single shot circuit to reduce the pulse width.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: April 1, 1986
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque
  • Patent number: 4554508
    Abstract: A carrier detection circuit includes a rectification stage, an integrator, a comparator, and a digital counter. By utilizing a digital counter, long time constants are provided without the use of external components. If desired, a mark detect circuit is used when a mark must be present to signify the presence of carrier. Hysteresis is provided by the comparator to insure that slight fluctuations in the carrier level do not affect the comparison.
    Type: Grant
    Filed: December 7, 1983
    Date of Patent: November 19, 1985
    Assignee: American Microsystems, Incorporated
    Inventor: Yusuf A. Haque
  • Patent number: 4540949
    Abstract: An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second inverting input lead (117b) receives an input signal to be amplified or compared.
    Type: Grant
    Filed: May 2, 1984
    Date of Patent: September 10, 1985
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque
  • Patent number: 4533876
    Abstract: A differential operational amplifier is provided with a feedback loop which continuously adjusts the common mode voltage level of the amplifier so that it lies in the center of the dynamic range of the amplifier. The feedback loop measures the instantaneous common mode voltage level and compares it with a reference voltage which is set to reflect the desired common mode voltage. An error signal is generated and fed back into the amplifier to adjust the instantaneous common mode voltage level towards the reference level. Frequency compensation is also provided to overcome the phase shift introduced by the use of RC networks.
    Type: Grant
    Filed: October 18, 1983
    Date of Patent: August 6, 1985
    Assignee: American Microsystems, Inc.
    Inventors: Yusuf Haque, Erwin Ofner
  • Patent number: 4475170
    Abstract: A programmable transversal filter utilizes a plurality of programmable multiplying means. The result of each multiplication is summed by a summing circuit, thus providing an output signal. The delay network comprises a plurality of signal sample and hold circuits which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. The filter also includes a plurality of reference sample and hold circuits which store error voltages equal to the error voltage component of the voltages provided by the signal sample and hold circuits.A first analog cross-point switch is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means.
    Type: Grant
    Filed: February 8, 1982
    Date of Patent: October 2, 1984
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque
  • Patent number: 4470126
    Abstract: A programmable transversal filter (10) utilizes a plurality of programmable multiplying means (M.sub.1 -M.sub.4). The result of each multiplication is summed by a summing circuit (7), thus providing an output signal (y(t)). The delay network of this invention comprises a plurality of sample and hold circuits (S.sub.1 -S.sub.4) which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods.An analog cross-point switch (51) is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means.
    Type: Grant
    Filed: October 29, 1981
    Date of Patent: September 4, 1984
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque
  • Patent number: 4460874
    Abstract: An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second inverting input lead (117b) receives an input signal to be amplified or compared.
    Type: Grant
    Filed: August 14, 1981
    Date of Patent: July 17, 1984
    Assignee: American Microsystems, Incorporated
    Inventor: Yusuf A. Haque
  • Patent number: 4441082
    Abstract: An AGC circuit (12) contains a programmable gain stage comprising an operational amplifier (150) and one or more capacitor arrays (101, 121) for controlling the closed loop gain of the operational amplifier. The output signal (V.sub.O) of this operational amplifier is rectified, and the rectified signal is alternately integrated with a reference voltage (V.sub.ref) of opposite polarity to the rectified AGC signal. The polarity of the integrated voltages operates a counter stage (200). The output bits (0.sub.2 -0.sub.N) of the counter are used to control switches (134-2 through 134-N, 135-2 through 135-N, 110-2 through 110-N, 111-2 through 111-N) in the one or more capacitor arrays which control the closed loop gain of the operational amplifier of the AGC circuit of this invention.
    Type: Grant
    Filed: October 9, 1981
    Date of Patent: April 3, 1984
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque