Patents by Inventor Yusuke Fukumura

Yusuke Fukumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9858181
    Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: January 2, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Uematsu, Satoshi Muraoka, Hiroshi Kakita, Akio Idei, Yusuke Fukumura, Satoru Watanabe, Takayuki Ono, Taishi Sumikura, Yuichi Fukuda, Takashi Miyagawa, Michinori Naito, Hideki Osaka, Masabumi Shibata, Hitoshi Ueno, Kazunori Nakajima, Yoshihiro Kondo
  • Patent number: 9317312
    Abstract: A computer comprising: a processor; a memory; and an I/O device, the memory including at least one first memory element and at least one second memory element, wherein a memory area provided by the at least one second memory element includes a data storage area and a data compression area, wherein the computer comprises a virtualization management unit, and wherein the virtualization management unit is configured to: set a working set for storing data required for processing performed by a virtual machine in generating the virtual machine, and control data stored in the working set in such a manner that part of the data stored in the working set is stored in the data compression area based on a state of accesses to the data stored in the working set.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 19, 2016
    Assignee: HITACH, LTD
    Inventors: Nobukazu Kondo, Yusuke Fukumura
  • Publication number: 20160092351
    Abstract: A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed.
    Type: Application
    Filed: June 20, 2013
    Publication date: March 31, 2016
    Inventors: Yutaka UEMATSU, Satoshi MURAOKA, Hiroshi KAKITA, Akio IDEI, Yusuke FUKUMURA, Satoru WATANABE, Takayuki ONO, Taishi SUMIKURA, Yuichi FUKUDA, Takashi MIYAGAWA, Michinori NAITO, Hideki OSAKA, Masabumi SHIBATA, Hitoshi UENO, Kazunori NAKAJIMA, Yoshihiro KONDO
  • Publication number: 20140250286
    Abstract: A computer comprising: a processor; a memory; and an I/O device, the memory including at least one first memory element and at least one second memory element, wherein a memory area provided by the at least one second memory element includes a data storage area and a data compression area, wherein the computer comprises a virtualization management unit, and wherein the virtualization management unit is configured to: set a working set for storing data required for processing performed by a virtual machine in generating the virtual machine, and control data stored in the working set in such a manner that part of the data stored in the working set is stored in the data compression area based on a state of accesses to the data stored in the working set.
    Type: Application
    Filed: February 26, 2014
    Publication date: September 4, 2014
    Applicant: HITACH, LTD
    Inventors: Nobukazu KONDO, Yusuke FUKUMURA
  • Publication number: 20140067900
    Abstract: A stream processing device executes query processing with respect to data included in a packet input from a network with a duplication unit that duplicates the input packet into a plurality of packets, a protocol processing unit that executes protocol processing corresponding to the network with respect to one packet among the duplicated packets to determine whether or not an error is present, a storage unit that stores a management flag indicating a result of the protocol processing, a data extraction unit that extracts data necessary for the query processing from another packet among the duplicated packets, a query processing unit that executes the query processing with respect to the extracted data, and outputs data including a result of the query processing. An output control unit determines whether to output the data output from the query processing unit from the stream processing device on the basis of the management flag.
    Type: Application
    Filed: August 5, 2013
    Publication date: March 6, 2014
    Applicant: HITACHI, LTD.
    Inventor: Yusuke FUKUMURA
  • Patent number: 8185570
    Abstract: The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Fukumura, Patrick Hamilton, Masaya Nakahata, Takashi Oomori
  • Publication number: 20080215660
    Abstract: The three-term input floating-point adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent with a width of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, a carry save adder (CSA) which reduces the mantissas from the pre-processing circuit from three terms to two terms, a carry look-ahead adder (CLA) which carries out addition on the mantissas of the two terms, a normalization circuit which makes a left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which output
    Type: Application
    Filed: December 13, 2007
    Publication date: September 4, 2008
    Inventors: Yusuke Fukumura, Patrick Hamilton, Masaya Nakahata, Takashi Oomori