Abstract: In one embodiment, a liquid crystal display device includes a lens array unit having a cylindrical lens array constituted by a plurality of cylindrical lenses each having a lens surface and a generatrix corresponding to the lens surface. The lens surface is arranged in a line in a direction orthogonally crossing the generatrix. A first substrate is arranged at a back side of the lens array unit and includes a pixel electrode in a belt shape extending in a different direction from the direction in which the generatrix extends. The pixel electrode is formed in a V character shape. A second substrate is arranged between the lens array unit and the first substrate including a counter electrode in a belt shape commonly arranged on the pixel electrodes extending in a parallel direction to the pixel electrode.

Abstract: In one embodiment, a liquid crystal display device comprises a pixel electrode including a first main electrode disposed between a first line and a second line and extending like a belt in a first extending direction. A first counter electrode includes a second main electrode extending like a belt in the first extending direction, a second counter electrode having a third main electrode extending like a belt in the first extending direction. The second and third main electrodes are disposed on both sides of the first main electrode, and an initial alignment direction of the liquid crystal molecules is parallel with a direction passing through an interstice between the first end side of the first main electrode and the second line, and through an interstice between the second end side of the first main electrode and the first line.

Abstract: By using switching power supplies a, b, and n, which have detection function of over-current, over-voltage and low voltage, in the case where a short-circuit occurred in a load which is connected to output of a switching power supply, and in the case where a MOSFET of the switching power supply is in a short-circuit state and broken, a main power is forced to be off, and a failure log of the switching power supply is stored in a non-volatile memory unit EEPROM; and also in the case where the main power was turned off and on, even if an abnormal log of the switching power supply logged in the non-volatile memory unit, reclosing of the main power is suppressed and which of the switching power supply occurred failure is notified to the outside.

Abstract: In one embodiment, a first substrate includes a pixel electrode having a first main electrode in a belt-like shape extending along a first cross line direction which crosses at an acute angle in a counterclockwise direction with respect to an initial alignment direction of liquid crystal molecules, and a second main electrode in the belt-like shape extending along a second cross line direction which crosses at an acute angle in a clockwise direction with respect to the initial alignment direction of the liquid crystal molecules. A second substrate includes a counter electrode having a pair of third main electrodes in the belt-like shape arranged above a pair of regions sandwiching the first main electrode extending along a first cross line direction and a pair of fourth main electrodes in the belt-like shape arranged above a pair of regions sandwiching the second main electrode extending along the second cross line direction.

Abstract: A rotor of a rotary machine includes a rotary shaft, a rotor core fixed to a circumferential surface of the rotary shaft, a plurality of permanent magnets arranged on a circumferential surface of the rotor core at specific intervals along a circumferential direction thereof, conducting circuits arranged to surround the permanent magnets, and magnetic material pieces arranged on outer surfaces of the individual permanent magnets. Each of the conducting circuits includes a pair of first conductor sections arranged between magnetic poles formed by the adjacent permanent magnets and a pair of second conductor sections electrically connecting the first conductor sections.

Abstract: A compact, light permanent magnet motor with low torque pulsations is obtained by reducing a cogging torque resulting from variations at the end of a rotor, such as an error in attachment position and a variation in magnet characteristic of the permanent magnets. A permanent magnet rotating electrical machine includes a rotor having a rotor core and plural magnetic poles formed of permanent magnets provided to the rotor core, and a stator having plural teeth opposing the plural magnetic poles, a stator core provided with slots in which to store an armature winding wire wound around the teeth, and supplemental grooves provided to the teeth in portions opposing the rotor in an axial direction of the stator core.

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

Abstract: In one embodiment, a liquid crystal display device includes a first substrate and a second substrate. In the first substrate, gate lines extend in a first direction, and a first source line and a second source line extend in a second direction orthogonally crossing the first direction. A pixel electrode having a first belt-like main electrode is arranged approximately in a central portion between the first source line and the second source line and extending in the second direction. A first belt-like sub-electrode covers the gate line between the first source line and the second source line and extending in the first direction. The second substrate includes a counter electrode having a second main electrode arranged on the first and second source lines and extending in the second direction. A liquid crystal layer is held between the first substrate and the second substrate.

Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

Abstract: Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

Abstract: In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

Abstract: It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip. The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.

Abstract: There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

Abstract: Provided is a permanent magnet type motor including: a rotor including a rotor core and a plurality of permanent magnets; a conducting circuit including a first electric conductor extending in an axial direction of the rotor and being disposed between permanent magnets in a circumferential direction of the rotor and a second electric conductor for connecting the first electric conductors electrically; and a stator disposed so as to be opposed to the rotor, including a stator core and an armature winding. A rotation angle is detected by measuring current flowing in the armature winding. The stator core is formed to have a shape in which, a slot pitch is defined by ?s=(2×?×Rs)/Ns, where an inner radius of the stator is represented by Rs and a number of slots is represented by Ns, a value Wsn obtained by dividing a slot opening width Ws by the slot pitch ?s satisfies “0.08?Wsn”.

Abstract: An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).

Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

Abstract: A rotor of a rotary machine includes a rotary shaft, a rotor core fixed to a circumferential surface of the rotary shaft, a plurality of permanent magnets arranged on a circumferential surface of the rotor core at specific intervals along a circumferential direction thereof, conducting circuits arranged to surround the permanent magnets, and magnetic material pieces arranged on outer surfaces of the individual permanent magnets. Each of the conducting circuits includes a pair of first conductor sections arranged between magnetic poles formed by the adjacent permanent magnets and a pair of second conductor sections electrically connecting the first conductor sections.

Abstract: By using switching power supplies a, b, and n, which have detection function of over-current, over-voltage and low voltage, in the case where a short-circuit occurred in a load which is connected to output of a switching power supply, and in the case where a MOSFET of the switching power supply is in a short-circuit state and broken, a main power is forced to be off, and a failure log of the switching power supply is stored in a non-volatile memory unit EEPROM; and also in the case where the main power was turned off and on, even if an abnormal log of the switching power supply logged in the non-volatile memory unit, reclosing of the main power is suppressed and which of the switching power supply occurred failure is notified to the outside.