Patents by Inventor Yusuke Nonaka

Yusuke Nonaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190073159
    Abstract: A storage controller measures a RAID group (RG) operating time, which is the operating time of an RG. The storage controller then corrects the measured RG operating time, which is used to calculate the operating rate of the RG, on the basis of a correction coefficient associated with the type of the physical devices (PDEVs) constituting the RG, and on the basis of the RG backend multiplicity, which is the multiplicity of the I/O commands transmitted to the RG.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 7, 2019
    Applicant: HITACHI, LTD.
    Inventors: Takao YOSHIKAWA, Yusuke NONAKA, Jin CHOI, Masahide KAWARASAKI
  • Publication number: 20190067614
    Abstract: To increase emission efficiency of a fluorescent light-emitting element by efficiently utilizing a triplet exciton generated in a light-emitting layer. The light-emitting layer of the light-emitting element includes at least a host material and a guest material. The triplet exciton generated from the host material in the light-emitting layer is changed to a singlet exciton by triplet-triplet annihilation (TTA). The guest material (fluorescent dopant) is made to emit light by energy transfer from the singlet exciton. Thus, the emission efficiency of the light-emitting element is improved.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yusuke NONAKA, Satoshi SEO, Harue OSAKA, Tsunenori SUZUKI, Takeyoshi WATABE
  • Patent number: 10153346
    Abstract: To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target. In that case, partial pressure of water in a deposition chamber before or in the deposition is set to be lower than or equal to 10?3 Pa, preferably lower than or equal to 10?4 Pa, more preferably lower than or equal to 10?5 Pa. Thus, a dense oxide semiconductor film is obtained. The density of the oxide semiconductor film is higher than 6.0 g/cm3 and lower than 6.375 g/cm3.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Yusuke Nonaka, Hiroshi Kanemura
  • Patent number: 10128455
    Abstract: To increase emission efficiency of a fluorescent light-emitting element by efficiently utilizing a triplet exciton generated in a light-emitting layer. The light-emitting layer of the light-emitting element includes at least a host material and a guest material. The triplet exciton generated from the host material in the light-emitting layer is changed to a singlet exciton by triplet-triplet annihilation (TTA). The guest material (fluorescent dopant) is made to emit light by energy transfer from the singlet exciton. Thus, the emission efficiency of the light-emitting element is improved.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yusuke Nonaka, Satoshi Seo, Harue Osaka, Tsunenori Suzuki, Takeyoshi Watabe
  • Publication number: 20180308989
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Application
    Filed: June 28, 2018
    Publication date: October 25, 2018
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Kengo AKIMOTO, Hiroki OHARA, Tatsuya HONDA, Takatsugu OMATA, Yusuke NONAKA, Masahiro TAKAHASHI, Akiharu MIYANAGA
  • Patent number: 10103277
    Abstract: A method comprising a step of forming an oxide semiconductor film over a substrate by a sputtering method while heating the substrate at a temperature of higher than 200° C. and lower than or equal to 400° C. is provided. The oxide semiconductor film comprises a crystalline region and is in a non-single-crystal state. The step of forming the oxide semiconductor film is performed by using a sputtering target comprising indium, gallium, zinc and oxygen and a sputtering gas comprising at least one of a rare gas and oxygen.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Publication number: 20180269323
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Inventors: Akihiro SHIMIZU, Nagatoshi OOKI, Yusuke NONAKA, Katsuhiko ICHINOSE
  • Publication number: 20180269418
    Abstract: An object of one embodiment of the present invention is to provide a multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance, a separation layer containing a substance having a hole-transport property and a substance having an electron-transport property, and a second light-emitting layer containing two kinds of organic compounds that form an exciplex and a substance that can convert triplet excitation energy into luminescence. Note that a light-emitting element in which light emitted from the first light-emitting layer has an emission spectrum peak on the shorter wavelength side than an emission spectrum peak of the second light-emitting layer is more effective.
    Type: Application
    Filed: May 18, 2018
    Publication date: September 20, 2018
    Inventors: Nobuharu Ohsawa, Yusuke Nonaka, Takahiro Ishisone, Satoshi Seo, Takuya Kawata
  • Publication number: 20180261788
    Abstract: Provided is a light-emitting element which includes a first electrode, a second electrode over the first electrode, and first and second light-emitting layers therebetween. The first light-emitting layer contains a first host material and a first light-emitting material, and the second light-emitting layer contains a second host material and a second light-emitting material. The first light-emitting material is a fluorescent material, and the second light-emitting material is a phosphorescent material. The level of the lowest triplet excited state (T1 level) of the first light-emitting material is higher than the T1 level of the first host material. A light-emitting device, an electronic device, and a lighting device including the light-emitting element are further provided.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 13, 2018
    Inventors: Takahiro ISHISONE, Satoshi SEO, Yusuke NONAKA, Nobuharu OHSAWA
  • Patent number: 10067882
    Abstract: A storage system manages correspondence relationships between physical addresses and logical addresses inside a storage device, as well as logical spaces provided by a plurality of storage devices, and when a determination is made as to whether first data and second data are stored in the same storage device in a case in which the first data and the second data are exchanged inside a logical space, and the determination is found to be affirmative, the storage device replaces the logical address corresponding to the first data with the logical address corresponding to the second data without changing the physical address of the physical area in which the first data is stored and the physical address of the physical area in which the second data is stored.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: September 4, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Miho Imazaki, Akira Yamamoto, Yusuke Nonaka, Tomohiro Yoshihara, Shunji Kawamura
  • Publication number: 20180240993
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Application
    Filed: April 17, 2018
    Publication date: August 23, 2018
    Inventors: Satoshi SEO, Takahiro ISHISONE, Nobuharu OHSAWA, Yusuke NONAKA, Toshiki SASAKI
  • Publication number: 20180233588
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Patent number: 10026917
    Abstract: An object of one embodiment of the present invention is to provide a multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance, a separation layer containing a substance having a hole-transport property and a substance having an electron-transport property, and a second light-emitting layer containing two kinds of organic compounds that form an exciplex and a substance that can convert triplet excitation energy into luminescence. Note that a light-emitting element in which light emitted from the first light-emitting layer has an emission spectrum peak on the shorter wavelength side than an emission spectrum peak of the second light-emitting layer is more effective.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: July 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Nobuharu Ohsawa, Yusuke Nonaka, Takahiro Ishisone, Satoshi Seo, Takuya Kawata
  • Publication number: 20180182988
    Abstract: A light-emitting element includes a stack of a first light-emitting layer emitting fluorescent light and a second light-emitting layer emitting phosphorescent light between a pair of electrodes. The second light-emitting layer includes a first layer in which an exciplex is formed, a second layer in which an exciplex is formed, and a third layer in which an exciplex is formed. The second layer is located over the first layer, and the third layer is located over the second layer. An emission peak wavelength of the second layer is longer than an emission peak wavelength of the first layer and an emission peak wavelength of the third layer.
    Type: Application
    Filed: February 21, 2018
    Publication date: June 28, 2018
    Inventors: Takuya KAWATA, Nobuharu OHSAWA, Yusuke NONAKA, Takahiro ISHISONE, Satoshi SEO
  • Publication number: 20180173721
    Abstract: This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.
    Type: Application
    Filed: July 27, 2015
    Publication date: June 21, 2018
    Applicant: Hitachi, Ltd.
    Inventors: Akihiko ARAKI, Yusuke NONAKA, Noboru MORISHITA
  • Patent number: 9978971
    Abstract: Emission efficiency of a light-emitting element is improved. The light-emitting element has a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material and a host material. The second light-emitting layer includes a phosphorescent material, a first organic compound, and a second organic compound. An emission spectrum of the second light-emitting layer has a peak in a yellow wavelength region. The first organic compound and the second organic compound form an exciplex.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone, Nobuharu Ohsawa, Yusuke Nonaka, Toshiki Sasaki
  • Patent number: 9978869
    Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimizu, Nagatoshi Ooki, Yusuke Nonaka, Katsuhiko Ichinose
  • Publication number: 20180114061
    Abstract: An image processing method causing an image processing device to execute a process including: obtaining a first image and a second image captured at different timings for an identical inspection target by passing through an imaging range of an image sensor row; extracting respective feature points of the first image and the second image; associating the feature points of the first image and the feature points of the second image with each other; estimating a conversion formula to convert the feature point of the second image to the feature point of the first image based on a restraint condition of a quadratic equation, in accordance with respective coordinates of three or more sets of the feature points associated between the first image and the second image; and converting the second image into a third image corresponding to the first image based on the estimated conversion formula.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 26, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke NONAKA, Eigo Segawa
  • Patent number: 9946655
    Abstract: In a storage system, first and second controllers have respective first and second buffer and cache areas. The first controller stores write data in accordance with a write request in the first cache area without involving the first buffer area and to transfer the stored write data to the second cache area without involving the second buffer area. The first controller is configured to determine which of the first and second cache areas is to be used as a copy source and to be used as a copy destination depending on whether the storing of the first write data in the first cache area had been successful or on whether the transfer of the write data from the first cache area to the second controller had been successful, and by copying data from the copy source to the copy destination, recovers data in an area related to a transfer failure.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 17, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Morishita, Shintaro Kudo, Yusuke Nonaka, Akira Yamamoto
  • Patent number: 9947777
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi