Patents by Inventor Yuta Yoshida

Yuta Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424575
    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: September 24, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
  • Patent number: 10391779
    Abstract: A liquid discharge apparatus includes a plurality of liquid discharge heads to discharge liquid, and a plurality of head tanks communicating with the plurality of liquid discharge heads, respectively. Each of the plurality of head tanks includes a liquid chamber to store the liquid and a gas chamber separated from the liquid chamber by a diaphragm, and the gas chamber of one of the plurality of head tanks communicates with the gas chamber of another of the plurality of head tanks.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: August 27, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Tomomi Katoh, Yuta Moriwaki, Satoru Yoshida
  • Patent number: 10388366
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Publication number: 20190193199
    Abstract: A laser processing apparatus includes a laser oscillator oscillating a laser beam, a light condensing lens condensing the laser beam oscillated by the laser oscillator, and a mask member disposed between the laser oscillator and the light condensing lens and blocking part of the laser beam oscillated by the laser oscillator, in which the mask member includes a transmitting portion through which light passes, and a reflecting film surrounding the transmitting portion and reflecting the part of the laser beam.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 27, 2019
    Inventor: Yuta YOSHIDA
  • Patent number: 10211104
    Abstract: A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral surplus region, a holding step of holding the package wafer in such a manner that the grooves are exposed, an orientation adjustment step of causing the grooves to be parallel to a processing-feed direction in which processing feeding of a chuck table is carried out when dividing grooves are formed, a coordinate registration step of imaging both ends of the plural grooves exposed at a peripheral edge and registering coordinate information of both ends or a single side of the grooves from taken images, and a dividing groove forming step of calculating the positions of the dividing grooves to be formed along the grooves based on the registered coordinate information of the grooves and forming the dividing grooves along the grooves.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: February 19, 2019
    Assignee: Disco Corporation
    Inventors: Yuta Yoshida, Hironari Ohkubo
  • Patent number: 10198826
    Abstract: The present invention provides a method for accurately and simply measuring a blade width (W) of a blade tip section (1) of a grooving tool mounted on a machine tool.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 5, 2019
    Assignee: O-M LTD.
    Inventors: Hiroki Inui, Dai Ito, Hirofumi Nakakubo, Katsunori Kabasawa, Yuta Yoshida
  • Publication number: 20180261280
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 13, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Shinji TANAKA, Makoto YABUUCHI, Yuta YOSHIDA
  • Publication number: 20180214986
    Abstract: A laser processing apparatus includes: a chuck table that holds a packaged wafer by a holding surface; a laser processing unit that applies a laser beam to the packaged wafer to form a through-groove along each division line; an X-axis moving unit that moves the chuck table in an X-axis direction; and an examination unit. The chuck table includes: a holding member that forms the holding surface; and a light emitting body. The examination unit includes: a line sensor that extends in a Y-axis direction; and a control unit that determines the result of processing through reception by the line sensor of light from the light emitting body through the through-groove. The line sensor images the whole surface of the packaged wafer being held by the chuck table.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 2, 2018
    Inventors: Yuri Ban, Yuta Yoshida, Kentaro Odanaka
  • Publication number: 20180211852
    Abstract: A laser processing apparatus includes: a chuck table that holds a packaged wafer; a laser beam applying unit that applies a pulsed laser beam to the packaged wafer; X-axis moving unit for moving the chuck table in an X-axis direction; an imaging unit that images the packaged wafer; and a control unit. The chuck table has a transparent or semi-transparent holding member and a light emitting body. The control unit includes: an imaging instruction section that causes the imaging unit to image the packaged wafer while the pulsed laser beam is being applied to the packaged wafer; and a determination section that determines the processed state of a through-groove from a picked-up image obtained according to an instruction by the imaging instruction section.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 26, 2018
    Inventors: Yuri Ban, Yuta Yoshida, Kentaro Odanaka
  • Patent number: 10002662
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 19, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Publication number: 20180061711
    Abstract: A processing method of a package wafer includes a mold resin removal step of exposing grooves filled with a mold resin of the package wafer in a peripheral surplus region, a holding step of holding the package wafer in such a manner that the grooves are exposed, an orientation adjustment step of causing the grooves to be parallel to a processing-feed direction in which processing feeding of a chuck table is carried out when dividing grooves are formed, a coordinate registration step of imaging both ends of the plural grooves exposed at a peripheral edge and registering coordinate information of both ends or a single side of the grooves from taken images, and a dividing groove forming step of calculating the positions of the dividing grooves to be formed along the grooves based on the registered coordinate information of the grooves and forming the dividing grooves along the grooves.
    Type: Application
    Filed: August 15, 2017
    Publication date: March 1, 2018
    Inventors: Yuta Yoshida, Hironari Ohkubo
  • Publication number: 20180053317
    Abstract: The present invention provides a method for accurately and simply measuring a blade width (W) of a blade tip section (1) of a grooving tool mounted on a machine tool.
    Type: Application
    Filed: July 31, 2017
    Publication date: February 22, 2018
    Applicant: O-M LTD.
    Inventors: Hiroki INUI, Dai ITO, Hirofumi NAKAKUBO, Katsunori KABASAWA, Yuta YOSHIDA
  • Publication number: 20180019013
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: September 27, 2017
    Publication date: January 18, 2018
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: SHINJI TANAKA, MAKOTO YABUUCHI, YUTA YOSHIDA
  • Patent number: 9831381
    Abstract: A package substrate machining method is provided. The package substrate includes a ceramic substrate, a plurality of device chips arranged on one face of the ceramic substrate, and a coating layer made of a resin that covers the entire one face of the ceramic substrate. The package substrate machining method includes a first laser-machined groove formation step adapted to form, in the coating layer, first laser-machined grooves along scheduled division lines set up on the package substrate by irradiating a laser beam at a wavelength absorbable by the coating layer from the coating layer side of the package substrate; and a second laser-machined groove formation step adapted to form, in the ceramic substrate and after the first laser-machined groove formation step, second laser-machined grooves along the scheduled division lines by irradiating a laser beam from the ceramic substrate side of the package substrate.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 28, 2017
    Assignee: Disco Corporation
    Inventor: Yuta Yoshida
  • Publication number: 20170338118
    Abstract: A laser processing apparatus has a laser beam applying unit for applying a laser beam to a workpiece held on a chuck table. The laser beam applying unit includes an elliptical spot forming member for changing the spot shape of a pulsed laser beam into an elliptical shape and making the major axis of the elliptical beam spot parallel to a feeding direction, a diffractive optical element for branching the pulsed laser beam having the elliptical beam spot obtained by the elliptical spot forming member, into a plurality of pulsed laser beams each having an elliptical beam spot whose major axis extends in the feeding direction, and a condensing lens for condensing each of the pulsed laser beams branched by the diffractive optical element to the workpiece in such a manner that the major axes of the elliptical beam spots of the pulsed laser beams branched are partially overlapped.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 23, 2017
    Inventor: Yuta Yoshida
  • Patent number: 9799396
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 24, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Publication number: 20170301664
    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 19, 2017
    Inventors: Yuta YOSHIDA, Makoto YABUUCHI, Yoshisato YOKOYAMA
  • Publication number: 20170084327
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Publication number: 20170077347
    Abstract: A package substrate machining method is provided. The package substrate includes a ceramic substrate, a plurality of device chips arranged on one face of the ceramic substrate, and a coating layer made of a resin that covers the entire one face of the ceramic substrate. The package substrate machining method includes a first laser-machined groove formation step adapted to form, in the coating layer, first laser-machined grooves along scheduled division lines set up on the package substrate by irradiating a laser beam at a wavelength absorbable by the coating layer from the coating layer side of the package substrate; and a second laser-machined groove formation step adapted to form, in the ceramic substrate and after the first laser-machined groove formation step, second laser-machined grooves along the scheduled division lines by irradiating a laser beam from the ceramic substrate side of the package substrate.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 16, 2017
    Inventor: Yuta Yoshida
  • Patent number: 9542999
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida