Patents by Inventor Yutaka Akiyama

Yutaka Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10870661
    Abstract: The present invention provides a novel compound having antiviral activity, especially HIV replication inhibitory activity and a medicament containing the same. The compound represented by the formula: wherein A3 is CR3A, CR3AR3B, N or NR3C; R3A, R3B, R4A and R4B are each independently a hydrogen atom, halogen, cyano, substituted or unsubstituted alkyl, substituted or unsubstituted alkynyl, or substituted or unsubstituted non-aromatic carbocyclyl; R3C is a hydrogen atom, substituted or unsubstituted alkyl, or substituted or unsubstituted non-aromatic carbocyclyl; ring T1 is substituted or unsubstituted nitrogen-containing non-aromatic heterocycle; R1 is a hydrogen atom, halogen, cyano, or substituted or unsubstituted alkyl; R2 is each independently substituted or unsubstituted alkyl or the like: n is 1 or 2; R3 is substituted or unsubstituted aromatic carbocyclyl or the like; R4 is a hydrogen atom or a carboxy protecting group.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 22, 2020
    Assignee: Shionogi & Co., Ltd.
    Inventors: Yoshinori Tamura, Shuichi Sugiyama, Akira Matsumura, Toshiyuki Akiyama, Yutaka Tomida
  • Publication number: 20200173044
    Abstract: A method for producing a transparent electrode for oxygen production having a Ta nitride layer on a transparent substrate, including: a step of forming a Ta nitride precursor layer on the transparent substrate; and a step of nitriding the Ta nitride precursor layer with a mixed gas containing ammonia and a carrier gas.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Applicants: Mitsubishi Chemical Corporation, THE UNIVERSITY OF TOKYO, JAPAN TECHNOLOGICAL RESEARCH ASSOCIATION OF ARTIFICIAL PHOTOSYNTHETIC CHEMICAL PROCESS, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hiroshi NISHIYAMA, Tomohiro HIGASHI, Yutaka SASAKI, Taro YAMADA, Kazunari DOMEN, Yohichi SUZUKI, Seiji AKIYAMA
  • Publication number: 20200123005
    Abstract: A method includes a step of forming a sacrificial layer on a first film, a step of forming a second film on the sacrificial layer, a step of forming an etching opening that extends through at least one of the first film and the second film so as to communicate with the sacrificial layer, and a step of forming a hollow portion by etching the sacrificial layer using a gas containing a fluorine-containing gas and hydrogen via the etching opening, wherein a composition ratio of silicon to nitrogen in a first region having a face in contact with the sacrificial layer is larger than a composition ratio of silicon to nitrogen in a second region not including the first region.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Takayuki Sumida, Ayako Maruyama, Takahiro Akiyama, Yutaka Setomoto
  • Publication number: 20200055873
    Abstract: The present invention provides a novel compound having antiviral activity, especially HIV replication inhibitory activity and a medicament containing the same. The compound represented by the formula: wherein A3 is CR3A, CR3AR3B, N or NR3C; R3A, R3B, R4A and R4B are each independently a hydrogen atom, halogen, cyano, substituted or unsubstituted alkyl, substituted or unsubstituted alkynyl, or substituted or unsubstituted non-aromatic carbocyclyl; R3C is a hydrogen atom, substituted or unsubstituted alkyl, or substituted or unsubstituted non-aromatic carbocyclyl; ring T1 is substituted or unsubstituted nitrogen-containing non-aromatic heterocycle; R1 is a hydrogen atom, halogen, cyano, or substituted or unsubstituted alkyl; R2 is each independently substituted or unsubstituted alkyl or the like: n is 1 or 2; R3 is substituted or unsubstituted aromatic carbocyclyl or the like; R4 is a hydrogen atom or a carboxy protecting group.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Applicant: Shionogi & Co., Ltd.
    Inventors: Yoshinori Tamura, Shuichi Sugiyama, Akira Matsumura, Toshiyuki Akiyama, Yutaka Tomida
  • Patent number: 10494380
    Abstract: The present invention provides a novel compound having antiviral activity, especially HIV replication inhibitory activity and a medicament containing the same. The compound represented by the formula: wherein A3 is CR3A, CR3AR3B, N or NR3C; R3A, R3B, R4A and R4B are each independently a hydrogen atom, halogen, cyano, substituted or unsubstituted alkyl, substituted or unsubstituted alkynyl, or substituted or unsubstituted non-aromatic carbocyclyl; R3C is a hydrogen atom, substituted or unsubstituted alkyl, or substituted or unsubstituted non-aromatic carbocyclyl; ring T1 is substituted or unsubstituted nitrogen-containing non-aromatic heterocycle; R1 is a hydrogen atom, halogen, cyano, or substituted or unsubstituted alkyl; R2 is each independently substituted or unsubstituted alkyl or the like: n is 1 or 2; R3 is substituted or unsubstituted aromatic carbocyclyl or the like; R4 is a hydrogen atom or a carboxy protecting group.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 3, 2019
    Assignee: Shionogi & Co., Ltd.
    Inventors: Yoshinori Tamura, Shuichi Sugiyama, Akira Matsumura, Toshiyuki Akiyama, Yutaka Tomida
  • Patent number: 10475918
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Publication number: 20190165165
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Inventors: Tohru KAWAI, Yasutaka NAKASHIBA, Yutaka AKIYAMA
  • Patent number: 10236371
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Publication number: 20180102360
    Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.
    Type: Application
    Filed: December 8, 2017
    Publication date: April 12, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Yasutaka NAKASHIBA, Yutaka AKIYAMA
  • Patent number: 9871036
    Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: January 16, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Yutaka Akiyama
  • Publication number: 20170125581
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Tohru KAWAI, Yasutaka NAKASHIBA, Yutaka AKIYAMA
  • Patent number: 9606012
    Abstract: An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: March 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yutaka Akiyama, Yasutaka Nakashiba
  • Patent number: 9564426
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Publication number: 20160204099
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Application
    Filed: November 4, 2015
    Publication date: July 14, 2016
    Inventors: Tohru KAWAI, Yasutaka NAKASHIBA, Yutaka AKIYAMA
  • Patent number: 9385230
    Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: July 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimomura, Yutaka Akiyama, Saya Shimomura, Yasutaka Nakashiba
  • Publication number: 20160066415
    Abstract: A multilayer wiring board includes an insulating layers stacked on one another, lands formed on an upper surface part of the multilayer wiring board, and a differential transmission line formed on or in each of the insulating layer. An electronic component is mounted on the lands. The differential transmission line is constituted of a pair of signal lines which extend from the lands toward a signal receiving end. Each of the signal lines is provided with an open stub which extends in a stacking direction of the insulating layers, and has a same width as a width of the signal lines, one end of the open stub being connected to a corresponding one of the signal lines, and another end of the open stub being open.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 3, 2016
    Inventors: Ryohei KATAOKA, Kouji KONDOH, Jyun AKIMICHI, Kanji OTSUKA, Yutaka AKIYAMA, Kaoru HASHIMOTO
  • Patent number: 9240237
    Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 19, 2016
    Assignee: NAGASE & CO., LTD.
    Inventors: Kanji Otsuka, Yoichi Sato, Yutaka Akiyama, Fumiaki Fujii, Tatsuya Nagasawa, Minoru Uwai
  • Publication number: 20150325696
    Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.
    Type: Application
    Filed: July 21, 2015
    Publication date: November 12, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Akihiro SHIMOMURA, Yutaka AKIYAMA, Saya SHIMOMURA, Yasutaka NAKASHIBA
  • Patent number: 9117903
    Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 25, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Shimomura, Yutaka Akiyama, Saya Shimomura, Yasutaka Nakashiba
  • Publication number: 20150070957
    Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.
    Type: Application
    Filed: December 26, 2013
    Publication date: March 12, 2015
    Inventors: Kanji Otsuka, Yoichi Sato, Yutaka Akiyama, Fumiaki Fujii, Tatsuya Nagasawa, Minoru Uwai