Abstract: An information processing device configured to present a virtual space at a display mounted on the head of a user, the information processing device inputs detection information from a sensor that detects movement of the head of the user. The information processing device generates the virtual space including a body image representing at least a part of a body of the user in response to the detection information. The information processing device inputs correction information from a device operated to perform correction of an angle in a pitch direction of the head of the user. The information processing device corrects a pitch direction angle employed when presenting the virtual space at the display based on the correction information. The information processing device presents the virtual space at the display with the corrected pitch direction angle.

Abstract: A prediction device extracts each predictive feature vector expressing a feature from a peptide that is a target for biostability prediction. The prediction device generates a predicted value of biostability of the prediction target cyclic peptide by inputting plural predictive feature vectors into a trained model pre-trained to output a predicted value of peptide biostability.

Abstract: A prediction device extracts each predictive feature vector expressing a feature from a peptide that is a target for membrane permeability prediction. The prediction device generates a predicted value of membrane permeability of the prediction target peptide by inputting plural predictive feature vectors into a trained model pre-trained to output a predicted value of peptide membrane permeability.

Abstract: In response to request signals transmitted from a terminal, a server generates prediction information relating to pharmacokinetics of a peptide. The server then transmits the prediction information to the terminal.

Abstract: An information processing device configured to present a virtual space at a display mounted on the head of a user, the information processing device inputs detection information from a sensor that detects movement of the head of the user. The information processing device generates the virtual space including a body image representing at least a part of a body of the user in response to the detection information. The information processing device inputs correction information from a device operated to perform correction of an angle in a pitch direction of the head of the user. The information processing device corrects a pitch direction angle employed when presenting the virtual space at the display based on the correction information. The information processing device presents the virtual space at the display with the corrected pitch direction angle.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract: A multilayer wiring board includes an insulating layers stacked on one another, lands formed on an upper surface part of the multilayer wiring board, and a differential transmission line formed on or in each of the insulating layer. An electronic component is mounted on the lands. The differential transmission line is constituted of a pair of signal lines which extend from the lands toward a signal receiving end. Each of the signal lines is provided with an open stub which extends in a stacking direction of the insulating layers, and has a same width as a width of the signal lines, one end of the open stub being connected to a corresponding one of the signal lines, and another end of the open stub being open.

Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.