Patents by Inventor Yutaka Hayashi

Yutaka Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160326323
    Abstract: A fiber-reinforced resin material includes a thermoplastic resin and a bundle of reinforced fibers arranged in one direction, the thermoplastic resin being a reactive resin. The thermoplastic resin may be an epoxy resin. The reinforced fibers may be carbon fibers. A molded fiber-reinforced resin body is obtained using the fiber-reinforced resin material. The molded fiber-reinforced resin body may be formed by the application of heat and pressure.
    Type: Application
    Filed: January 8, 2015
    Publication date: November 10, 2016
    Applicant: KOMATSU SEIREN CO., LTD.
    Inventors: Yutaka HAYASHI, Taketoshi NAKAYAMA, Hiroyuki YAMADA, Honami NODA
  • Patent number: 9403720
    Abstract: A porous ceramic for which any decrease in water permeability can be suppressed over a long period of time. A porous ceramic is composed of a porous ceramic sintered body produced by molding and sintering a mixture containing a clay, wherein a surface portion of the porous ceramic sintered body has been removed by grinding. The mixture preferably contains a foaming agent.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 2, 2016
    Assignee: KOMATSU SEIREN CO., LTD.
    Inventors: Teruhiro Okuya, Yutaka Hayashi, Kohsuke Togashi, Akihisa Kaneda, Takeshi Ohta
  • Publication number: 20160193608
    Abstract: A biochip support member is provided that comprises a base material, and a columnar member different member from the base material having a support area that can support a biochip formed of a biomolecule provided at one end, and is attached to the base material through an attaching part at the other end.
    Type: Application
    Filed: February 25, 2016
    Publication date: July 7, 2016
    Applicant: NIKON CORPORATION
    Inventors: Tadao ISAMI, Yutaka HAYASHI, Takehito UEDA
  • Patent number: 9362328
    Abstract: The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 7, 2016
    Assignees: National Institute of Advanced Industrial Science and Technology, RICOH COMPANY, LTD.
    Inventors: Takaaki Negoro, Hirofumi Watanabe, Yutaka Hayashi, Toshitaka Ota, Yasushi Nagamune
  • Publication number: 20160144368
    Abstract: This plate (100) is provided with a board (130) having a first surface, and partitioned member (120) in which a plurality of partitions are formed by dividing walls (22). Gaps (28) are formed to the first surface side between neighboring dividing walls (22). The ends of the dividing walls (22) at the gap (28) side have welded portions welded to the first surface of the board (130), the board (130) and the partitioned member (120) being welded at the welded portions.
    Type: Application
    Filed: January 29, 2016
    Publication date: May 26, 2016
    Applicant: NIKON CORPORATION
    Inventors: Tadao ISAMI, Muneki HAMASHIMA, Takehito UEDA, Yutaka HAYASHI
  • Patent number: 9343721
    Abstract: Provided is a separator for non-aqueous batteries, capable of being usefully used in non-aqueous batteries, and a non-aqueous battery equipped with this separator. The separator for non-aqueous batteries includes: a base layer comprising a fiber aggregate, and an electrolyte-swellable resin layer formed on at least one surface of the base layer, the resin layer comprising a urethane resin (C) obtained by reacting a polyol (A) including a vinyl polymer (a1) and a polyether polyol (a2) with a polyisocyanate (B). The vinyl polymer (a1) has as a main chain a vinyl polymer (a1?) having two hydroxyl groups at one of the termini of the main chain, and a polyoxyethylene chain having a number average molecular weight of 200 to 800 as a side chain, the percentage of the polyoxyethylene chain based on the vinyl polymer (a1) being within the range of 70 mass % to 98 mass %.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: May 17, 2016
    Assignee: KURARAY CO., LTD.
    Inventors: Tomohiro Hayakawa, Takayoshi Hosoya, Hiroyuki Kawai, Hideo Hayashi, Yutaka Hayashi, Kohsuke Togashi, Naotaka Gotoh
  • Patent number: 9337234
    Abstract: A photoelectric converter includes a first pn junction comprised of at least two semiconductor regions of different conductivity types, and a first field-effect transistor including a first source connected with one of the semiconductor regions, a first drain, a first insulated gate and a same conductivity type channel as that of the one of the semiconductor regions. The first drain is supplied with a second potential at which the first pn junction becomes zero-biased or reverse-biased relative to a potential of the other of the semiconductor regions. When the first source turns to a first potential and the one of the semiconductor regions becomes zero-biased or reverse-biased relative to the other semiconductor regions, the first pn junction is controlled not to be biased by a deep forward voltage by supplying a first gate potential to the first insulated gate, even when either of the semiconductor regions is exposed to light.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: May 10, 2016
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, RICOH COMPANY, LTD.
    Inventors: Yutaka Hayashi, Toshitaka Ota, Yasushi Nagamune, Hirofumi Watanabe, Takaaki Negoro, Kazunari Kimino
  • Publication number: 20160059201
    Abstract: A biochip fixing method includes: arranging a biochip on an object with a predetermined material interposed therebetween; and irradiating the predetermined material with energy waves via the object to fix the biochip to the object.
    Type: Application
    Filed: March 14, 2014
    Publication date: March 3, 2016
    Applicant: NIKON CORPORATION
    Inventors: Takehiko UEDA, Yutaka HAYASHI, Tadao ISAMI, Muneki HAMASHIMA
  • Patent number: 9236569
    Abstract: A storage element includes a first electrode and a second electrode separated by a gap and a dielectric layer provided between the first electrode and the second electrode to fill the gap. A separation distance of the gap changes in response to application of a voltage to a space between the first electrode and the second electrode, such that a switching phenomenon is produced which switches a resistance state between the first electrode and the second electrode between a high resistance state in which it is difficult for tunnel current to flow and a low resistance state in which it is easy for tunnel current to flow.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 12, 2016
    Assignee: Funai Electric Co., Ltd.
    Inventors: Shigeo Furuta, Yuichiro Masuda, Tsuyoshi Takahashi, Masatoshi Ono, Yutaka Hayashi, Taro Itaya, Yasuhisa Naitoh, Tetsuo Shimizu
  • Patent number: 9197220
    Abstract: A reset method of an photoelectric conversion device at least including a phototransistor having a first collector, a first base, and a first emitter, and a first field-effect transistor having a first source, a first drain, and a first gate, includes: connecting the first base, and one of the first source and the first drain of the first field-effect transistor by having a common region, or a continuous region, without a base electrode; supplying a base reset potential to the other of the first source and the first drain; and overlapping a time in which a first emitter potential is supplied to the first emitter and a time in which a first ON-potential that turns on the first field-effect transistor is supplied to the first gate.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: November 24, 2015
    Assignees: National Institute of Advanced Industrial Science and Technology, RICOH COMPANY, LTD.
    Inventors: Yutaka Hayashi, Toshitaka Ota, Yasushi Nagamune, Hirofumi Watanabe, Takaaki Negoro, Kazunari Kimino
  • Patent number: 9190145
    Abstract: In a drive method for a memory element that includes an insulating substrate, a first electrode and a second electrode provided on the insulating substrate, and an inter-electrode gap portion provided between the first electrode and the second electrode and having a gap of the order of nanometers where a phenomenon of a change in resistance value between the first and second electrodes occurs, and that can perform a transition from a predetermined low-resistance state to a predetermined high-resistance state and a transition from the high-resistance state to the low-resistance state, a current pulse is applied to the memory element by a constant current circuit upon the transition from the high-resistance state to the low-resistance state.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 17, 2015
    Assignees: National Institute of Advanced Industrial Science and Technology, Funai Electric Co., Ltd.
    Inventors: Tsuyoshi Takahashi, Yuichiro Masuda, Shigeo Furuta, Touru Sumiya, Masatoshi Ono, Yutaka Hayashi, Toshimi Fukuoka, Tetsuo Shimizu, Kumaragurubaran Somu, Hiroshi Suga, Yasuhisa Naitou
  • Patent number: 9142579
    Abstract: In order to achieve a photoelectric conversion cell and an array of high sensitivity and high dynamic range, there is a need for a photoelectric conversion cell and an array in which combination of an amplified photoelectric conversion element and a selection element are resistant to external noise, and the combination is resistant to effects from address selection pulse noise at array readout time. In the present invention, in order to solve the problem, a photoelectric conversion cell has been configured with a combination of an amplified photoelectric conversion element (100) and a selection element (10 and the like) which are resistant to external noise, and various means of solution of the combination are provided which are resistant to the effects of address selection pulse noise at array readout time. As a result, a dynamic range of 6 to 7 orders of magnitude for light detection has become possible.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: September 22, 2015
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yutaka Hayashi, Yasushi Nagamune, Toshitaka Ota
  • Patent number: 9135990
    Abstract: A memory element includes an insulating substrate; a first electrode and a second electrode on the insulating substrate; and an inter-electrode gap portion that causes a change in resistance value between the first and second electrodes. Applied to the memory element from a pulse generating source is a first voltage pulse for shifting from a predetermined low-resistance state to a predetermined high-resistance state, and a second voltage pulse for shifting from the high-resistance state to the low-resistance state through a series-connected resistor, by which current flowing to the memory element after the change to a low resistance value is reduced. When shifting from the high to the low-resistance state, a voltage pulse is applied such that an electrical resistance between the pulse generating source and the memory element becomes higher than the electrical resistance shifting from the low to the high-resistance state.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 15, 2015
    Assignees: National Institute of Advanced Industrial Science and Technology, Funai Electric Co., Ltd.
    Inventors: Tsuyoshi Takahashi, Yuichiro Masuda, Shigeo Furuta, Touru Sumiya, Masatoshi Ono, Yutaka Hayashi, Toshimi Fukuoka, Tetsuo Shimizu, Kumaragurubaran Somu, Hiroshi Suga, Yasuhisa Naitou
  • Patent number: 9130159
    Abstract: Disclosed is a fabrication method of an element with nanogap electrodes including a first electrode, a second electrode provided above the first electrode, and a gap provided between the first electrode and the second electrode, the gap being in an order of nanometer to allow resistive state to be switched by applying a predetermined voltage between the first electrode and the second electrode, the method comprising: forming the first electrode; forming a spacer on an upper surface of the first electrode; forming the second electrode in contact with an upper surface of the spacer; and removing the spacer to form the gap.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: September 8, 2015
    Assignee: Funai Electric Co., Ltd.
    Inventors: Shigeo Furuta, Touru Sumiya, Yuichiro Masuda, Tsuyoshi Takahashi, Yutaka Hayashi, Masatoshi Ono
  • Publication number: 20150205314
    Abstract: A semiconductor integrated circuit that is used for a stabilizing power supply circuit which supplies an output power supply voltage to a parallel connection of a smoothing capacitor and a load, from an input power supply voltage, includes an error amplifier that detects an error of the output power supply voltage, an output control circuit that is connected between the input terminal and the output terminal, a phase compensation circuit that is connected to the error amplifier, and a detection control circuit that is connected to the phase compensation circuit.
    Type: Application
    Filed: January 9, 2015
    Publication date: July 23, 2015
    Inventors: Kentaro HAYASHI, Yutaka Hayashi
  • Patent number: 9059065
    Abstract: Provided is a method of varying the gain of an amplifying photoelectric conversion device and a variable gain photoelectric conversion device which are capable of achieving both signal processing under low illuminance and high-current processing under high light intensity, and thereby capable of securing a wide dynamic range. An amplifying photoelectric conversion part includes a photoelectric conversion element and amplification transistors forming a Darlington circuit. The sources and the drains of field-effect transistors are connected to the bases and the emitters of the amplification transistors, respectively. The gates of the field-effect transistors each function as a gain control part.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 16, 2015
    Assignees: National Institute of Advanced Industrial Science and Technology, RICOH COMPANY, LTD.
    Inventors: Yutaka Hayashi, Kazuhiro Yoneda, Hirofumi Watanabe, Katsuhiko Aisu, Takaaki Negoro, Toshitaka Ota, Yasushi Nagamune
  • Publication number: 20150145583
    Abstract: The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value.
    Type: Application
    Filed: February 3, 2015
    Publication date: May 28, 2015
    Inventor: Yutaka HAYASHI
  • Publication number: 20150123069
    Abstract: A storage element includes a first electrode and a second electrode separated by a gap and a dielectric layer provided between the first electrode and the second electrode to fill the gap. A separation distance of the gap changes in response to application of a voltage to a space between the first electrode and the second electrode, such that a switching phenomenon is produced which switches a resistance state between the first electrode and the second electrode between a high resistance state in which it is difficult for tunnel current to flow and a low resistance state in which it is easy for tunnel current to flow.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 7, 2015
    Inventors: Shigeo FURUTA, Yuichiro MASUDA, Tsuyoshi TAKAHASHI, Masatoshi ONO, Yutaka HAYASHI, Taro ITAYA, Yasuhisa NAITOH, Tetsuo SHIMIZU
  • Publication number: 20150075065
    Abstract: The invention provides a processing method for upgrading an organic phase substance by removing heavy element species from the organic phase substance originating from a resource substance in mild environmental conditions, and further provides a method for collecting removed heavy element species and a method for collecting other substances.
    Type: Application
    Filed: October 24, 2014
    Publication date: March 19, 2015
    Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Tooru Nakamura, Yutaka Hayashi, Akira Suzuki, Richard Brommeland, Andrew Myles
  • Patent number: 8975940
    Abstract: The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Hayashi