Abstract: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film formed on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor thin film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. A conductive thin film is connected with the second region and the third region. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: An insulated gate transistor has a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type disposed in contact with the semiconductor thin film. A gate threshold voltage of the first conductive gate is controlled by a forward bias of the third semiconductor region with respect to one of the first and second semiconductor regions.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

Abstract: According to the present invention, there is provided a bearing apparatus for a wheel of vehicle comprising a hub wheel integrally formed therewith a wheel mounting flange on the periphery at one end thereof, and a double row rolling bearing, the double row rolling bearing comprising an outer member integrally formed therewith a body mounting flange on the periphery thereof and also formed therewith double row outer raceway surfaces, an inner member including said hub wheel and formed therewith double row inner raceway surfaces each arranged opposite to each of said double row outer surfaces, and double row rolling elements freely rotatably contained between said double row outer and second raceway surfaces, said double row rolling bearing being adapted to be applied a predetermined preload characterized in that: there are arranged a separate outer or inner ring on at least one of said outer and inner members, and a preload varying means arranged at an abutting portion between said outer and inner members for

Abstract: An exposure apparatus transfers a pattern of a mask onto a substrate and includes a covering member which is disposed in the exposure apparatus and which substantially isolates a predetermined spacing from outside gas. The covering member includes a first thin film made of a first material which blocks penetration of the outside gas with respect to the predetermined spacing and a second thin film having a low degasification property and made of a second material of at least one of a metal and an inorganic substance. An exposure method transfers a pattern of a mask onto a substrate and includes the steps of isolating a part spacing of an optical path spacing for an exposure beam which transfers the pattern of the mask onto the substrate from outside gas by using such a covering member.

Abstract: In a non-volatile memory in which a floating gate is provided above a single crystal control region, a potential of wiring, which is arranged above the floating gate, has a capacitive coupling with respect to the floating gate, or even one part in and on an insulating film on the floating gate is included or attached with electric charge, thereby varying the gate threshold voltage of the floating gate non-volatile memory measured from the single crystal control region. In order to solve the above-described problems, the present invention provides following methods. A shield conductive film is provided above a floating gate through a shield insulating film.

Abstract: An insulated gate transistor is comprised of a semiconductor thin film, a first gate insulating film formed on a main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulating film, first and second confronting semiconductor regions of a first conductivity type insulated from the first conductive gate and disposed in contact with the semiconductor thin film, and a third semiconductor region of a second conductivity type opposite to the first conductivity type and disposed in contact with the semiconductor thin film. The insulated gate transistor is controlled by injecting carriers of the second conductivity type into the semiconductor thin film from the third semiconductor region, and thereafter applying a first electric potential to the first conductive gate to form a channel of the first conductivity type on a portion of the semiconductor thin film disposed between the first semiconductor region and the second semiconductor region.

Abstract: Submitted herewith is a check in the amount of $650.00 to cover the additional fee for thirteen (13) claims in excess of twenty total. Should the check prove insufficient for any reason or should an additional fee be due, authorization is hereby given to charge any such deficiency or additional fee to our Deposit Account No. 01-0268.

Abstract: A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor or a process technique for a standard power supply voltage of the IC or LSI. In order to increase an operating voltage of a field effect transistor, measures are taken in which a gate is divided into division gates, and electric potentials which are closer to a drain electric potential and which change according to increase or decrease in the drain electric potential are supplied to the division gates nearer a drain, respectively.

Abstract: A high voltage operating field effect transistor is formed in an IC or LSI by utilizing a constituent portion of a transistor for a standard power supply voltage of the IC or LSI or by utilizing it's process technique. In order to increase an operating voltage of a field effect transistor, a measure is taken in which a gate is provided with an electric potential distribution varying in accordance with the drain electric potential.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density.

Abstract: The present invention provides a polishing apparatus with a construction which makes it possible to prevent the peripheral portions of a substrate from sloping downward as a result of the polishing member tilting at the peripheral portions of the substrate during the polishing of the substrate, and which makes it possible to adjust the contact pressure quickly in accordance with changes in the contact area between the polishing surface and the substrate surface.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: The present invention aims to provide a luminous sheet that emits sufficient light and provides enough luminance to enable recognition, is lightweight and pliable, and for which application and working are simple. The present invention further aims to provide a production method for this luminous sheet. The luminous sheet according to the present invention comprises a light reflecting layer and a luminescent layer in which a luminescent agent is included in the range of (40˜400 g/m2)×(coverage ratio % /100%).

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

Abstract: The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.

Abstract: A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

Abstract: Low thermal expansion ceramics contains a cordierite crystal phase, wherein a phase of a crystalline compound containing at least one element selected from the group consisting of an alkaline earth element other than Mg, a rare earth element, Ga and In, is precipitated in the grain boundaries of said crystal phase, said ceramics has a relative density of not smaller than 95%, a coefficient of thermal expansion of not larger than 1×10?6/° C. at 10 to 40° C., and a Young's modulus of not smaller than 130 GPa. That is, the ceramics has a small coefficient of thermal expansion, is deformed very little depending upon a change in the temperature, has a very high Young's modulus and is highly rigid and is resistance against external force such as vibration. Accordingly, the ceramics is very useful as a member for supporting a wafer or an optical system is a lithography apparatus that forms high resolution circuit patterns on a silicon wafer.