Patents by Inventor Yutaka Itoh
Yutaka Itoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12214709Abstract: A vehicle transport planning device includes a transport proposal unit that proposes, to an occupant of a vehicle equipped with an internal combustion engine, transport of the vehicle in a predetermined area where driving of the internal combustion engine is prohibited or restricted, and a transport arrangement unit that requests arrangement of a vehicle transport device for transporting the vehicle when the occupant desires the transport of the vehicle.Type: GrantFiled: November 9, 2022Date of Patent: February 4, 2025Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masayuki Itoh, Iwao Maeda, Tatsuya Sugano, Norinao Watanabe, Yutaka Nakamura, Yoshikazu Jikuhara, Yuki Nishikawa, Yuta Maniwa
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Patent number: 8841753Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: March 23, 2012Date of Patent: September 23, 2014Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Patent number: 8810039Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: December 12, 2011Date of Patent: August 19, 2014Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8736067Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.Type: GrantFiled: July 27, 2011Date of Patent: May 27, 2014Assignee: Panasonic CorporationInventors: Hiroshige Hirano, Yukitoshi Ota, Yutaka Itoh
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Publication number: 20140061920Abstract: A semiconductor device includes: a first insulating film formed on a semiconductor substrate; a first interconnect formed on the first insulating film; a second insulating film formed on the first insulating film to cover the first interconnect; and a second interconnect formed on the second insulating film. The second interconnect includes a barrier layer formed on the second insulating film, and a plated layer formed on the barrier layer. The barrier layer prevents diffusion of atoms forming the plated layer into the second insulating film, and has a greater width than the plated layer.Type: ApplicationFiled: November 12, 2013Publication date: March 6, 2014Applicant: PANASONIC CORPORATIONInventors: Hiroshige HIRANO, Yutaka ITOH, Hiroyuki ISHIDA, Kazuhiro ISHIKAWA
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Patent number: 8237281Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: January 4, 2011Date of Patent: August 7, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Publication number: 20120181670Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Patent number: 8164163Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.Type: GrantFiled: February 12, 2008Date of Patent: April 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Koji Koike
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Publication number: 20120080780Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: Panasonic CorporationInventors: Koji TAKEMURA, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8139466Abstract: A recording/reproducing device (A) includes: a first device (31) for performing recording and/or reproduction of data with respect to a first detachable storage medium; a second device (35) for performing recording and/or reproduction of data with respect to a second detachable storage medium; a first display section (41) for notifying a working state of the first device (31); and a second display section (47) for notifying a working state of the second device (35). A relative positions of the first device (31) to the second device (35) is the same as a relative position of the first display section (41) to the second display section (47).Type: GrantFiled: September 5, 2005Date of Patent: March 20, 2012Assignee: Sharp Kabushiki KaishaInventors: Makoto Hashimoto, Hiroshi Minematsu, Akihisa Matsumoto, Shohji Takada, Kimiyoshi Itoh, Harumi Sakamoto, Noriaki Itai, Seiji Usami, Yutaka Itoh, Shuhki Ohtani, Hiroshi Mikuni
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Patent number: 8113644Abstract: A sensor reciprocates in a main scanning direction to detect lateral end portions of a sheet conveyed in a sub-scanning direction. A print head is mounted on a carriage reciprocating in the main scanning direction. A sheet-information acquiring unit acquires sheet information including a type and a size of the sheet. A positional-information storing unit stores positional information on lateral positions of the sheet on the conveying belt, corresponding to the size of the sheet. A control unit controls, when the type of the sheet is a pattern-printed sheet, a printing by the print head based on the positional information corresponding to the size of the sheet.Type: GrantFiled: September 24, 2008Date of Patent: February 14, 2012Assignee: Ricoh Company, Ltd.Inventors: Kazuya Tashiro, Yutaka Itoh
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Publication number: 20120025394Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.Type: ApplicationFiled: July 27, 2011Publication date: February 2, 2012Inventors: Hiroshige Hirano, Yukitoshi Ota, Yutaka Itoh
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Patent number: 8102056Abstract: A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.Type: GrantFiled: August 29, 2006Date of Patent: January 24, 2012Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Masao Takahashi, Hikari Sano, Yutaka Itoh, Koji Koike
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Patent number: 8070252Abstract: An image forming apparatus includes a transport belt, a carriage, a reflection sensor, and a control unit. The transport belt transports a recording sheet in a sub-scanning direction. The carriage, mounting a recording head, reciprocally moves in a main scanning direction to record an image on the recording sheet. The reflection sensor, mounted on the carriage, receives light reflected from the transport belt to detect a leading edge of the recording sheet, and outputs a detection signal corresponding to the received light. The control unit controls a contamination check process. The control unit instructs the carriage to move to a given position over the transport belt and to drive the transport belt for one rotation while maintaining the carriage at the given position. The control unit determines whether contamination exists on the transport belt based on the detection signal output from the reflection sensor.Type: GrantFiled: February 22, 2008Date of Patent: December 6, 2011Assignee: Ricoh Company, Ltd.Inventors: Yutaka Itoh, Kazuya Tashiro
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Publication number: 20110095430Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Patent number: 7896457Abstract: An ink-jet recording apparatus includes a sensor serving as a unit that detects a position of a trailing end of a recording sheet and a control unit serving as a unit that generates a layout of an image to be recorded. The control unit decides a position of the trailing end of the recording sheet based on a result of the sensor detection and layout information, calculates a recordable area, and performs control for not recording an image in areas other than the recordable area. A CPU in the control unit corrects the result of the sensor detection in deciding a position of the trailing end of the recording sheet.Type: GrantFiled: November 20, 2006Date of Patent: March 1, 2011Assignee: Ricoh Company, LimitedInventor: Yutaka Itoh
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Patent number: 7888801Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: GrantFiled: April 27, 2009Date of Patent: February 15, 2011Assignee: Panasonic CorporationInventors: Koji Takemura, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike
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Patent number: 7845753Abstract: An image forming device prints an image on a recording sheet by performing a reciprocating movement of a print head in a main scanning direction while transporting the recording sheet intermittently in a transporting direction. The image forming device is arranged to select one of a measurement value and a theoretical value based on a result of comparison between the measurement value and the theoretical value, so that the selected value is used as a value that indicates a rear-end position of the recording sheet.Type: GrantFiled: January 28, 2009Date of Patent: December 7, 2010Assignee: Ricoh Company, Ltd.Inventor: Yutaka Itoh
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Patent number: 7635413Abstract: A SiC single crystal is produced by the solution growth method in which a seed crystal attached to a seed shaft is immersed in a solution of SiC dissolved in a melt of Si or a Si alloy and a SiC single crystal is allowed to grow on the seed crystal by gradually cooling the solution or by providing a temperature gradient therein. To this method, accelerated rotation of a crucible is applied by repeatedly accelerating to a prescribed rotational speed and holding at that speed and decelerating to a lower rotational speed or a 0 rotational speed. The rotational direction of the crucible may be reversed each acceleration. The seed shaft may also be rotated synchronously with the rotation of the crucible in the same or opposite rotational as the crucible. A large, good quality single crystal having no inclusions are produced with a high crystal growth rate.Type: GrantFiled: March 1, 2007Date of Patent: December 22, 2009Assignee: Sumitomo Metal Industries, Ltd.Inventors: Kazuhiko Kusunoki, Kazuhito Kamei, Nobuyoshi Yashiro, Akihiro Yauchi, Yoshihisa Ueda, Yutaka Itoh, Nobuhiro Okada
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Publication number: 20090200677Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.Type: ApplicationFiled: April 27, 2009Publication date: August 13, 2009Applicant: PANASONIC CORPORATIONInventors: Koji TAKEMURA, Hiroshige Hirano, Yutaka Itoh, Hikari Sano, Masao Takahashi, Koji Koike