Patents by Inventor Yutaka Maruo

Yutaka Maruo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7667249
    Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: February 23, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Patent number: 7626225
    Abstract: A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, including: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region; the nonvolatile memory element further including a semiconductor layer, a separating insulation layer which is formed on the semiconductor layer and which demarcates a forming region of the nonvolatile memory element, a first diffusion layer which is formed on the semiconductor layer of the first region, a first source region and a first drain region formed on the first diffusion layer, a second diffusion layer which is separated from the first diffusion layer and which is formed on a periphery of the first diffusion layer and on the semiconductor layer of the second region, a second source region and a second drain region formed on the second diffusion layer, a third diffusion layer formed on the semiconductor layer of the third region, a first insulation layer formed above the
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: December 1, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yutaka Maruo
  • Patent number: 7612396
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: November 3, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Patent number: 7508019
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 24, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Patent number: 7482647
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: January 27, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Patent number: 7473962
    Abstract: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: January 6, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Yutaka Maruo, Susumu Inoue, Yo Takeda
  • Publication number: 20080067564
    Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.
    Type: Application
    Filed: October 24, 2007
    Publication date: March 20, 2008
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Patent number: 7304337
    Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: December 4, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Publication number: 20070246758
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Application
    Filed: June 26, 2007
    Publication date: October 25, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Susumu INOUE, Yo TAKEDA, Yutaka MARUO
  • Publication number: 20070246760
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Application
    Filed: June 26, 2007
    Publication date: October 25, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Susumu INOUE, Yo TAKEDA, Yutaka MARUO
  • Publication number: 20070246759
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Application
    Filed: June 26, 2007
    Publication date: October 25, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Susumu INOUE, Yo TAKEDA, Yutaka MARUO
  • Patent number: 7285764
    Abstract: An imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well storing the charges; a modulation transistor having a channel threshold voltage controlled by the stored charges and outputting a corresponding signal; a transfer control element having a control end coupled to a control end of the modulation transistor and controlling the potential barrier of a transfer channel between the accumulation and modulation wells, and controlling transfer of the charges; an unwanted electric charge discharging control element controlling the potential barrier of an unwanted electric charge discharging channel coupled to the accumulation well, and discharging charges overflowing from the accumulation well during a period except for the charges transfer period; and a residual charge discharging control element controlling the potential barrier of a residual electric charge discharging channel coupled to the modulation we
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: October 23, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Kazunobu Kuwazawa, Yutaka Maruo, Sanae Nishida, Yoshitaka Narita
  • Patent number: 7253462
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: August 7, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Publication number: 20060278914
    Abstract: A semiconductor device including a nonvolatile memory element, the nonvolatile memory element, including: a first region, a second region formed adjacent to the first region, and a third region formed adjacent to the second region; the nonvolatile memory element further including a semiconductor layer, a separating insulation layer which is formed on the semiconductor layer and which demarcates a forming region of the nonvolatile memory element, a first diffusion layer which is formed on the semiconductor layer of the first region, a first source region and a first drain region formed on the first diffusion layer, a second diffusion layer which is separated from the first diffusion layer and which is formed on a periphery of the first diffusion layer and on the semiconductor layer of the second region, a second source region and a second drain region formed on the second diffusion layer, a third diffusion layer formed on the semiconductor layer of the third region, a first insulation layer formed above the se
    Type: Application
    Filed: June 7, 2006
    Publication date: December 14, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Susumu INOUE, Yutaka MARUO
  • Publication number: 20060273373
    Abstract: A semiconductor device, includes: a non-volatile memory element, wherein the non-volatile memory element includes: a first region; a second region formed adjacent to the first region; and a third region formed adjacent to the second region; and the non-volatile memory element includes: a semiconductor layer; an isolation insulating layer provided on the semiconductor layer and defines a forming region of the non-volatile memory element; a first diffused layer formed on the semiconductor layer in the first region; a first source region and a first drain region formed on the first diffused layer; a second diffused layer spaced apart from the first diffused layer and formed on the semiconductor layer at a periphery of the first diffused layer and the second region; a third diffused layer formed on the semiconductor layer in the third region; a second source region and a second drain region formed on the third diffused layer; a first insulating layer formed above the semiconductor layer in the forming region of t
    Type: Application
    Filed: June 6, 2006
    Publication date: December 7, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Susumu Inoue, Yutaka Maruo
  • Patent number: 7126175
    Abstract: A semiconductor device comprising: a first light shielded region including a first semiconductor element, the first light shielded region being defined by a first light shielding wall provided in the periphery thereof; a second light shielded region including a second semiconductor element, the second light shielded region being defined by a second light shielding wall provided in the periphery thereof and being provided in a position adjacent to the first light shielded region; a first opening provided in the first light shielding wall; a second opening provided in the second light shielding wall and positioned facing to the first opening; a first wiring layer coupled with the first semiconductor element and brought out to the outside of the first light shielded region from the first opening; a second wiring layer coupled with the second semiconductor element and brought out to the outside of the second light shielded region from the second opening; and a light shielding film provided at least above a region
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: October 24, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Publication number: 20060170030
    Abstract: A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.
    Type: Application
    Filed: January 12, 2006
    Publication date: August 3, 2006
    Inventors: Yutaka Maruo, Susumu Inoue, Yo Takeda
  • Publication number: 20060138496
    Abstract: A semiconductor device comprising: a first light shielded region including a first semiconductor element, the first light shielded region being defined by a first light shielding wall provided in the periphery thereof; a second light shielded region including a second semiconductor element, the second light shielded region being defined by a second light shielding wall provided in the periphery thereof and being provided in a position adjacent to the first light shielded region; a first opening provided in the first light shielding wall; a second opening provided in the second light shielding wall and positioned facing to the first opening; a first wiring layer coupled with the first semiconductor element and brought out to the outside of the first light shielded region from the first opening; a second wiring layer coupled with the second semiconductor element and brought out to the outside of the second light shielded region from the second opening; and a light shielding film provided at least above a region
    Type: Application
    Filed: November 29, 2005
    Publication date: June 29, 2006
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Publication number: 20060131623
    Abstract: A semiconductor device includes: a semiconductor element provided on a semiconductor layer; a light-blocking wall provided around the semiconductor element; and a wiring layer electrically coupled to the semiconductor element and extended from an aperture not having the light-blocking wall to an outside of the light-blocking wall; wherein the wiring layer has a pattern containing a first section positioned in the aperture and a second section which has a width not narrower than a width of the aperture by providing a branched portion intersecting with an extension direction of the wiring layer; and wherein a surface of the branched portion facing outside of the light-blocking wall includes thereon a convex part.
    Type: Application
    Filed: November 28, 2005
    Publication date: June 22, 2006
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo
  • Publication number: 20060131626
    Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.
    Type: Application
    Filed: October 13, 2005
    Publication date: June 22, 2006
    Inventors: Susumu Inoue, Yo Takeda, Yutaka Maruo