Abstract: A solid-state imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well holding the charges from the accumulation well; a modulation transistor controlled by the charges held in the modulation well and that outputs a signal corresponding to the charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation and modulation wells to control transfer of the charges; an unwanted charges discharging control element controlling the potential barrier of an unwanted charges discharging channel coupled to the accumulation well, and discharging charges that overflow from the accumulation well during a period other than the transfer period when the photo-generated charges are transferred; and a residual charges discharging control element controlling the potential barrier of a residual charges discharging channel coupled to the modulation well, and discharging residua

Abstract: An imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well storing the charges; a modulation transistor having a channel threshold voltage controlled by the stored charges and outputting a corresponding signal; a transfer control element having a control end coupled to a control end of the modulation transistor and controlling the potential barrier of a transfer channel between the accumulation and modulation wells, and controlling transfer of the charges; an unwanted electric charge discharging control element controlling the potential barrier of an unwanted electric charge discharging channel coupled to the accumulation well, and discharging charges overflowing from the accumulation well during a period except for the charges transfer period; and a residual charge discharging control element controlling the potential barrier of a residual electric charge discharging channel coupled to the modulation we

Abstract: A solid-state imaging device comprising: a photoelectric conversion element generating photo-generated charges; an accumulation well accumulating the charges; a modulation well holding the charges from the accumulation well; a modulation transistor controlled by the charges held in the modulation well and that outputs a signal corresponding to the charges; a transfer control element changing the potential barrier of a transfer channel between the accumulation and modulation wells to control transfer of the charges; an unwanted charges discharging control element controlling the potential barrier of an unwanted charges discharging channel coupled to the accumulation well, and discharging charges that overflow from the accumulation well during a period other than the transfer period when the photo-generated charges are transferred; and a residual charges discharging control element controlling the potential barrier of a residual charges discharging channel coupled to the modulation well, and discharging residua

Abstract: Embodiments include semiconductor devices and a methods for manufacturing the same that suppress deficiencies in the transistor characteristics. A method for manufacturing a semiconductor device includes the steps of (A) forming a polishing stopper layer 14 having a predetermined pattern over a substrate 10, (B) removing a part of the substrate using the polishing stopper layer 14 as a mask to form a trench 16, (C) forming a trench oxide film 18 over a surface of the substrate 10 that forms the trench 16, (D) forming an insulating layer 21 that fills the trench 16 over an entire surface of the substrate, (E) polishing the insulating layer 21 by a chemical-mechanical polishing, (F) removing the polishing stopper layer 14, and (G) etching a part of the insulating layer 21 to form a trench insulating layer 20.

Abstract: A semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices (memory cells) are arranged in a matrix with a plurality of rows and columns. The nonvolatile semiconductor memory device includes a word gate formed on a semiconductor substrate with a first gate insulating layer interposed, an impurity diffusion layer formed in the semiconductor substrate which forms either a source region or a drain region, and first and second control gates in the shape of sidewalls formed along either side of the word gate. Each of the first and second control gates is disposed on the semiconductor substrate with a second gate insulating layer interposed, and also on the word gate with a side insulating layer interposed. The first and second control gates extend in the column direction. A pair of first and second control gates which are adjacent in the row direction is connected to a common contact section.

Abstract: A method of manufacturing a semiconductor integrated circuit device including a memory cell array in which non-volatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns.

Abstract: A method of manufacturing a semiconductor integrated circuit device having nonvolatile semiconductor memory devices includes the following steps (a) to (k): (a) A step of forming an element isolation region, (b) a step of forming a first gate insulating layer and a laminate including a first conductive layer for a word gate and having a plurality of openings extending in a first direction, (c) a step of forming second gate insulating layers, (d) a step of forming side insulating layers on both sides of the first conductive layer, (e) a step of forming a second conductive layer over the entire surface, (f) a step of forming a first mask layer at least in a region in which a common contact section is formed, (g) a step of anisotropically etching the second conductive layer, thereby forming first and second control gates in the shape of sidewalls and forming a contact conductive layer at least in a region in which the common contact section is formed, (h) a step of forming an impurity diffusion layer which forms

Abstract: A semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices (memory cells) are arranged in a matrix with a plurality of rows and columns. The nonvolatile semiconductor memory device includes a word gate formed on a semiconductor substrate with a first gate insulating layer interposed, an impurity diffusion layer formed in the semiconductor substrate which forms either a source region or a drain region, and first and second control gates in the shape of sidewalls formed along either side of the word gate. Each of the first and second control gates is disposed on the semiconductor substrate with a second gate insulating layer interposed, and also on the word gate with a side insulating layer interposed. The first and second control gates extend in the column direction. A pair of first and second control gates which are adjacent in the row direction is connected to a common contact section.

Abstract: A method for reducing implant-induced damage and residual photo-resist-induced damage to a gate insulator layer first forms a gate insulator layer on portions of a semiconductor substrate. A first gate electrode layer is formed over the gate insulator layer, this first gate electrode layer being thinner than the desired final gate electrode thickness. A threshold adjustment implant is performed through the first, thin, gate electrode layer and underlying gate insulator layer. A second gate electrode layer is formed over the first gate electrode layer such that the thickness of the first and second gate electrode layers are substantially equal to the desired final gate electrode thickness. The first and second gate electrode layers are then patterned concurrently by conventional photolithography processes to form the gate electrodes.

Abstract: A semiconductor memory and method of manufacture which are particularly useful for a high breakdown voltage EEPROM wherein high breakdown voltage transistors which are employed in a relatively large number and therefore greatly affect the integration density are formed with the masked offset structure, which is advantageous from the viewpoint of the integration density, while high breakdown voltage transistors which are not required in a large number and therefore have no large effect on the integration density are formed with the LOCOS offset structure, which requires a relatively small number of manufacturing steps and hence involves a relatively low production cost, and these two different types of transistors are fabricated on the same substrate. This arrangement enables optimization of the device structure in regard to miniaturization, reduction in the number or masks required and simplification of the manufacturing process.