Patents by Inventor Yutaka Ohta

Yutaka Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11143989
    Abstract: An image forming apparatus includes an image bearing member, a transfer member, a voltage source, a current detecting portion, a controller, and a receiving portion. During the recording material passing through the transfer portion, the controller controls a voltage applied to a transfer member on the basis of a detection result of the current detecting portion so that a current flowing through the transfer member falls within a predetermined range. The controller sets at least one of an upper limit and a lower limit of the predetermined range on the basis of a predetermined voltage changing instruction received by the receiving portion.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 12, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuya Ohta, Yutaka Kakehi, Toshiyuki Yamada
  • Patent number: 8860294
    Abstract: To provide a light emitting element, having: a lamination structure including a first conductive layer and a second conductive layer with a light emitting layer interposed between them; a groove structure in which the second conductive layer and the light emitting layer are divided into large and small two parts; a second conductive electrode pad that is electrically connected to the second conductive layer on the divided larger second conductive layer, a first conductive electrode pad on the divided smaller second conductive layer, and two or more electrical contacts connected to the first conductive layer so as to be independent from each other, by a conductive wiring extending to the first conductive layer, with the first conductive electrode pad as a start point.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: October 14, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tatsunori Toyota, Yutaka Ohta
  • Patent number: 8330168
    Abstract: An object of the present invention is to provide a nitride semiconductor light-emitting device in which contact resistance generated between an n-contact layer and an n-side electrode is effectively reduced while maintaining satisfactory external quantum efficiency, and a method of efficiently producing the nitride semiconductor light-emitting device. Specifically, the present invention characteristically provides a nitride semiconductor light-emitting device having a semiconductor laminated body including an n-type laminate, a light-emitting layer and a p-type laminate, and an n-side electrode and a p-side electrode, characterized in that: the n-type laminate includes an n-contact layer made of an AlxGa1-xN material (0.7?x?1.0) and an n-clad layer provided on the n-contact layer; and an interlayer made of an AlyGa1-yN material (0?y?0.5) is provided on a partially exposed portion, on the light-emitting layer side, of the n-contact layer.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: December 11, 2012
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yutaka Ohta, Yoshikazu Ooshika
  • Publication number: 20120299465
    Abstract: To provide a light emitting element, having: a lamination structure including a first conductive layer and a second conductive layer with a light emitting layer interposed between them; a groove structure in which the second conductive layer and the light emitting layer are divided into large and small two parts; a second conductive electrode pad that is electrically connected to the second conductive layer on the divided larger second conductive layer, a first conductive electrode pad on the divided smaller second conductive layer, and two or more electrical contacts connected to the first conductive layer so as to be independent from each other, by a conductive wiring extending to the first conductive layer, with the first conductive electrode pad as a start point.
    Type: Application
    Filed: December 8, 2010
    Publication date: November 29, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tatsunori Toyota, Yutaka Ohta
  • Publication number: 20110266553
    Abstract: An object of the present invention is to provide a nitride semiconductor light-emitting device in which contact resistance generated between an n-contact layer and an n-side electrode is effectively reduced while maintaining satisfactory external quantum efficiency, and a method of efficiently producing the nitride semiconductor light-emitting device. Specifically, the present invention characteristically provides a nitride semiconductor light-emitting device having a semiconductor laminated body including an n-type laminate, a light-emitting layer and a p-type laminate, and an n-side electrode and a p-side electrode, characterized in that: the n-type laminate includes an n-contact layer made of an AlxGa1-xN material (0.7?x?1.0) and an n-clad layer provided on the n-contact layer; and an interlayer made of an AlyGa1-yN material (0?y?0.5) is provided on a partially exposed portion, on the light-emitting layer side, of the n-contact layer.
    Type: Application
    Filed: December 24, 2009
    Publication date: November 3, 2011
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Yutaka Ohta, Yoshikazu Ooshika
  • Patent number: 7800096
    Abstract: A semiconductor element is disclosed having a layered body of a first conductivity type, a light emitting layer, a layered body of a second conductivity type, a constriction layer having a constriction hole, and a first electrode having a lighting hole, a second electrode positioned such that charge traveling between the first and second electrodes passes through the light emitting layer. The constriction hole area is larger than the lighting hole area, and the lighting hole and the constriction hole expose a part of the layered body of the second conductivity type. A mirror is positioned such that the mirror receives light emitted from the light emitting layer that passes through the layered body of the first conductivity type, and the mirror is constructed to have a high reflection ratio for light having peak wavelengths between 200 nm to 350 nm.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: September 21, 2010
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yutaka Ohta, Yoshikazu Oshika
  • Publication number: 20090250684
    Abstract: A semiconductor element is disclosed having a layered body of a first conductivity type, a light emitting layer, a layered body of a second conductivity type, a constriction layer having a constriction hole, and a first electrode having a lighting hole, a second electrode positioned such that charge traveling between the first and second electrodes passes through the light emitting layer. The constriction hole area is larger than the lighting hole area, and the lighting hole and the constriction hole expose a part of the layered body of the second conductivity type. A mirror is positioned such that the mirror receives light emitted from the light emitting layer that passes through the layered body of the first conductivity type, and the mirror is constructed to have a high reflection ratio for light having peak wavelengths between 200 nm to 350 nm.
    Type: Application
    Filed: March 5, 2009
    Publication date: October 8, 2009
    Applicant: Dowa Electronics Materials Co., Ltd
    Inventors: Yutaka Ohta, Yoshikazu Ooshika
  • Patent number: 6619415
    Abstract: It is the object of the present invention to increase the opening area of an air introducing opening without increasing running resistance. An air introducing opening is made at the front of an upper cowling, and side radiators and front forks are exposed to left and right sides behind the air introducing opening when viewed from the front side. Air guide walls overhanging the air introducing opening from the left and right sides of a nose portion and covering the front portion of the front forks are integrally formed with the cowling to guide running air to the side radiators.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: September 16, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroaki Hasumi, Yutaka Ohta
  • Patent number: 6422182
    Abstract: An engine cooling apparatus adopting a separate type radiator so as to make it possible to reduce the number of parts and simplify the internal structure of a water pump by connecting left and right radiators to a water pump. One end of a laterally-extending connecting pipe mounted across the engine in right and left directions is connected to a water pipe provided at an outlet tank of a left radiator, while the other end thereof is coupled with a joint pipe provided at an outlet tank of a right radiator. Water supplied from the left radiator flows through the laterally-extending connecting pipe and meets water flow from the right radiator in the outlet tank. A water pump sucks the water collected in the outlet tank through a water duct via a water pipe provided in the lower part of the outlet tank, and pressurizes the water and supplies it to a water jacket of the engine.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: July 23, 2002
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventor: Yutaka Ohta
  • Publication number: 20010014544
    Abstract: By perfectly preventing a particle from being attached on a silicon wafer or a silicon epitaxial wafer before and after the silicon epitaxial growth, pit formation on the silicon epitaxial layer in RCA cleaning is prevented from occurring. A pretreatment chamber, a vapor phase growth chamber and an aftertreatment chamber are mutually connected by a transport path whose interior is clean while being isolated from the outside environment. In the pretreatment chamber, megasonic cleaning using O3 added water is conducted (step S2); in the vapor growth chamber, removal of a chemical silicon oxide film C by pre-bake (step S4) and formation of a high quality silicon epitaxial layer E are conducted (step S5); and in the aftertreatment chamber, passivation of the silicon epitaxial layer E is conducted by O3 water cleaning or SC1 cleaning (step S7).
    Type: Application
    Filed: March 28, 2001
    Publication date: August 16, 2001
    Applicant: Shin-Etsu Handotai, Co., Ltd.
    Inventors: Norimichi Tanaka, Yutaka Ohta
  • Patent number: 6174740
    Abstract: A method for analyzing impurities within a silicon wafer in a convenient and simple manner with high accuracy and sensitivity. In a first example 1, a silicon wafer is subjected on its surface to a sandblasting process with use of powder of SiO2 and then to a thermal oxidation process in a dry-oxygen gas atmosphere to easily move impurities present within the silicon wafer into a distorted layer and to form a thermal oxide film and a surface layer of the wafer positioned directly therebelow and containing the distorted layer. The thermal oxide film or the surface layer containing the distorted layer is dissolved with, e.g., a solution of hydrofluoric acid to recover and analyze the dissolved solution. In a comparative example 1, the same processes as in the example 1 are carried out to analyze a predetermined solution, except that the sandblasting process is omitted.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: January 16, 2001
    Assignee: Shin-Etsu Handotai, Co., Ltd.
    Inventors: Yutaka Ohta, Hirofumi Nishijo, Akira Kosugi
  • Patent number: 5527612
    Abstract: A fluorocarbon copolymer-insulated wire comprising, around a conductor, an insulating layer made of a composition comprising an ethylene-tetrafluoroethylene copolymer and an unsintered tetrafluoroethylene-propylene copolymer, which is resistant to heat, abrasion and oil, and improved in flexibility. The wire can be efficiently installed in a narrow space in various equipments and enables easy wiring work.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: June 18, 1996
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Yutaka Ohta, Tamotsu Kaide, Kiyogo Nakagawa, Yosikazu Ebiike
  • Patent number: 5493455
    Abstract: A memory is provided in a tape cassette and it consists of a program information area for recording information on each program recorded on a tape and a tape information area for recording information on the entire tape. If this tape cassette is used by a video cassette recorder having a full function to drive the memory and by a video cassette recorder having a limited function to drive it, the program information recorded in the memory is consistent with the programs actually recorded on the tape. For example, a tape erasing prevention flag is set in the tape information area, while a program erasing prevention flag is set for each program in the program information area. In a different example, a tape inconsistency flag is set in the tape information area, while a program inconsistency flag is set for each program in the program information area. The data in the memory can be corrected by using such flags according to the programs actually recorded on the tape.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: February 20, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsutomu Miyoshi, Yutaka Ohta, Masako Sawada
  • Patent number: 5487358
    Abstract: A process for growing a silicon epitaxial layer on the main surface of a silicon substrate wafer using an apparatus for growing a silicon epitaxial layer is disclosed. The apparatus comprises a central injector passing a flow of a reactive gas past a central part of a horizontal chamber, peripheral injectors passing peripheral flows of the reactive gas past peripheral part of the chamber, a first controller controlling the mass flows of at least one of the silicon source, the dopant and hydrogen of the reactive gas fed by the central injector, and a second controller controlling the mass flows of at least one of the silicon source, the dopant and hydrogen fed by the peripheral injectors independently of the first controller. The process comprises control steps independently controlling the mass flows of the reactive gas by the first controller and the second controller.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: January 30, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Takatoshi Nagoya
  • Patent number: 5441571
    Abstract: A cylindrical apparatus for the growth of epitaxial layers having disposed inside a bell jar a susceptor provided thereon with pockets for retaining a substrate is disclosed. It allows the flow rate of a raw material gas inside the apparatus to be uniformized, the fluctuation of film thickness of epitaxial layers within one batch to be repressed below 5%, and the fluctuation of film thickness of an epitaxial layer in the substrate to be decreased by equalizing the gap area between the peripheral surface of the susceptor and the internal wall surface of the bell jar at least in the lateral wall portions of the bell jar confronting the substrates on the susceptor.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: August 15, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Yusho Hoshina, Takeshi Arai
  • Patent number: 5427052
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: June 27, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5421288
    Abstract: A process for growing a silicon epitaxial layer on the main surface of a silicon substrate wafer using an apparatus for growing a silicon epitaxial layer is disclosed. The apparatus comprises a central injector passing a flow of a reactive gas past a central part of a horizontal chamber, peripheral injectors passing peripheral flows of the reactive gas past a peripheral part of the chamber, a first controller controlling the mass flows of at least one of the silicon source, the dopant and hydrogen of the reactive gas fed by the central injector, and a second controller controlling the mass flows of at least one of the silicon source, the dopant and hydrogen fed by the peripheral injectors independently of the first controller. The process comprises control steps independently controlling the mass flows of the reactive gas by the first contoller and the second controller.
    Type: Grant
    Filed: December 9, 1993
    Date of Patent: June 6, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Takatoshi Nagoya
  • Patent number: 5393370
    Abstract: To provide a method of making a SOI film having a more uniform thickness in a SOI substrate which makes it possible to keep the variance at .+-.0.3 micrometers or less throughout the entire surface of the substrate, even for SOI substrates with a SOI film thickness between 1 micrometer and 10 micrometers. The surface of a SOI substrate is divided into a plurality of sections, then the SOI film thickness is measured for each section Wi (i=1-n) by means of the spectral interference method using an optical fiber cable, and, simultaneously, the SOI film is etched down to a prescribed thickness by a dry etching device, and thus a desired value and a variance (.+-.0.3 micrometers) of the SOI film thickness is obtained.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: February 28, 1995
    Assignee: Shin-Etsu Handotai Kabushiki Kaisha
    Inventors: Yutaka Ohta, Masatake Katayama, Isao Moroga
  • Patent number: 5376215
    Abstract: A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: December 27, 1994
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Ohta, Masatake Nakano, Masatake Katayama, Takao Abe
  • Patent number: 5336634
    Abstract: A dielectrically isolated substrate is comprised of a single-crystal silicon substrate or bond substrate and a single-crystal silicon substrate or base substrate bonded together into a composite structure. The bond substrate has a (110) plane as a main crystal plane and is provided with vertically walled moats and substantially squared islands positioned adjacent to the moats. The moats and islands result from anisotropic etching using a specific mask pattern. Also disclosed is a process for producing the composite structure.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: August 9, 1994
    Assignee: Shin-Etsu Handotui Co., Ltd.
    Inventors: Masatake Katayama, Makoto Sato, Yutaka Ohta, Mitsuru Sugita, Konomu Ohki