Patents by Inventor Yutaka Okazaki

Yutaka Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971491
    Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Yutaka Okazaki
  • Patent number: 10944014
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
  • Publication number: 20210057587
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Application
    Filed: August 31, 2020
    Publication date: February 25, 2021
    Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
  • Patent number: 10915438
    Abstract: A software-testing device includes a conversion unit configured to convert a PLC program for operating a programmable logic controller into a general-purpose language program described in a general-purpose programming language, and a test execution unit configured to perform a test on the general-purpose language program.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: February 9, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINEERING, LTD.
    Inventors: Hirotaka Okazaki, Noritaka Yanai, Masahiro Yamada, Yutaka Miyajima
  • Patent number: 10907668
    Abstract: A flow damper including a cylindrical vortex chamber, a small flow-rate pipe connected to a peripheral plate of the vortex chamber along a tangential direction, a large flow-rate pipe connected to the peripheral plate with a predetermined angle with respect to the small flow-rate pipe, an outlet pipe connected to an outlet formed in a central part of the vortex chamber, and a pressure equalization pipe with respective ends being connected to the peripheral plate on opposite sides of the outlet and at positions closer to a connection portion between the small flow-rate pipe and the large flow-rate pipe than positions facing each other, putting the outlet therebetween. The pressure equalization pipe is arranged with at least a part thereof is located at a higher position than a top plate of the vortex chamber, and an outgassing hole is provided at an uppermost part of the pressure equalization pipe.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 2, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Masamichi Iino, Shigeto Hirai, Taiki Asahara, Takafumi Ogino, Akira Kirita, Akihiro Toda, Hideyuki Sakata, Yutaka Tanaka, Setsuo Tokunaga, Takashi Nakahara, Takanori Okazaki
  • Patent number: 10900508
    Abstract: To include a cylindrical vortex chamber 35, a small flow-rate pipe 37 connected to a peripheral plate 35C of the vortex chamber 35 along a tangential direction thereof, a large flow-rate pipe 36 connected to the peripheral plate 35C with a predetermined angle with respect to the small flow-rate pipe 37, an outlet pipe connected to an outlet 39 formed in a central part of the vortex chamber 35, and a straightening plate 50 that is arranged in a part between the outlet 39 and the peripheral plate 35C of the vortex chamber 35, and when jets flow into the vortex chamber 35 from the small flow-rate pipe 37 and the large flow-rate pipe 36, straightens impinging jets from the small flow-rate pipe 37 and from the large flow-rate pipe 36 having flowed into the vortex chamber 35 toward the outlet 39.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 26, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hideyuki Sakata, Shigeto Hirai, Taiki Asahara, Takafumi Ogino, Akira Kirita, Akihiro Toda, Masamichi Iino, Toshihiro Sato, Yutaka Tanaka, Takanori Okazaki, Takashi Nakahara
  • Patent number: 10763373
    Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
  • Publication number: 20200258914
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Tomoaki MORIWAKA, Shinya SASAGAWA, Takashi OHTSUKI
  • Patent number: 10734487
    Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator over a substrate, an oxide over the first insulator, a second insulator over the oxide, a conductor overlapping with the oxide with the second insulator therebetween, a third insulator in contact with a top surface of the oxide, a fourth insulator in contact with a top surface of the third insulator, a side surface of the second insulator, and a side surface of the conductor, and a fifth insulator in contact with a side surface of the fourth insulator, a side surface of the third insulator, and the top surface of the oxide. The third insulator has a lower oxygen permeability than the fourth insulator.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Komagata, Naoki Okuno, Yutaka Okazaki, Hiroshi Fujiki
  • Publication number: 20200220028
    Abstract: A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Yutaka OKAZAKI
  • Patent number: 10685983
    Abstract: To provide a semiconductor device capable of retaining data for a long time. The semiconductor device includes a first transistor, an insulator covering the first transistor, and a second transistor over the insulator. The first transistor includes a first gate electrode, a second gate electrode overlapping with the first gate electrode, and a semiconductor between the first gate electrode and the second gate electrode. The first gate electrode is electrically connected to one of a source and a drain of the second transistor.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Yutaka Okazaki, Takahisa Ishiyama
  • Patent number: 10644039
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 5, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
  • Patent number: 10625717
    Abstract: A brake control device includes a mechanical brake output determination unit configured to determine the stage number of a braking force on the basis of a target deceleration of a moving body from one or a plurality of braking force stages output from a mechanical brake included in the moving body, a mechanical braking force estimation unit configured to estimate braking force of the mechanical brake corresponding to the stage number determined by the mechanical brake output determination unit, and a regenerative brake control unit configured to output a regenerative brake command value such that a regenerative brake included in the moving body outputs a braking force corresponding to a difference between target braking force based on the target deceleration and the braking force estimated by the mechanical braking force estimation unit.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: April 21, 2020
    Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINEERING, LTD.
    Inventors: Noritaka Yanai, Hirotaka Okazaki, Kazuyuki Wakasugi, Yutaka Miyajima
  • Patent number: 10522690
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Daisuke Matsubayashi, Yuichi Sato
  • Patent number: 10522689
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Publication number: 20190391910
    Abstract: A software-testing device includes a conversion unit configured to convert a PLC program for operating a programmable logic controller into a general-purpose language program described in a general-purpose programming language, and a test execution unit configured to perform a test on the general-purpose language program.
    Type: Application
    Filed: February 16, 2018
    Publication date: December 26, 2019
    Inventors: Hirotaka OKAZAKI, Noritaka YANAI, Masahiro YAMADA, Yutaka MIYAJIMA
  • Publication number: 20190355751
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Application
    Filed: May 28, 2019
    Publication date: November 21, 2019
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka OKAZAKI, Tomoaki Moriwaka, Shinya SASAGAWA, Takashi OHTSUKI
  • Patent number: 10483402
    Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10?5 ?·m or more and 4.8×10?3 ?·m or less.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yutaka Okazaki
  • Publication number: 20190341495
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Shunpei YAMAZAKI, Akihisa SHIMOMURA, Yuhei SATO, Yasumasa YAMANE, Yoshitaka YAMAMOTO, Hideomi SUZAWA, Tetsuhiro TANAKA, Yutaka OKAZAKI, Naoki OKUNO, Takahisa ISHIYAMA
  • Patent number: 10456918
    Abstract: A technique is provided, with which, even for an object which has a shape prone to be erroneously recognized and for which it is difficult to generate an initial value expected to produce a true value through fitting, it is possible to generate an appropriate initial value candidate through intuitive input and reduce erroneous recognition. An information processing apparatus includes a model acquiring unit configured to acquire a three-dimensional shape model of a target object, a display control unit configured to cause a display unit to display the three-dimensional shape model, a setting unit configured to set first and second orientations different from each other on the basis of the three-dimensional shape model displayed in the display unit, a parameter deriving unit configured to derive a transformation parameter that transforms the first orientation into the second orientation, and a storage unit configured to store the transformation parameter.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 29, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Daisuke Watanabe, Hiroshi Okazaki, Yutaka Niwayama