Patents by Inventor Yutaka Okazaki
Yutaka Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967649Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.Type: GrantFiled: August 25, 2022Date of Patent: April 23, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
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Publication number: 20240128380Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: ApplicationFiled: December 1, 2023Publication date: April 18, 2024Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
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Publication number: 20240105713Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.Type: ApplicationFiled: November 27, 2023Publication date: March 28, 2024Inventors: Tetsuhiro TANAKA, Yutaka OKAZAKI
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Patent number: 11901372Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: GrantFiled: March 23, 2023Date of Patent: February 13, 2024Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
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Publication number: 20240008342Abstract: A display device with high resolution is provided. The display device includes a plurality of light-emitting elements that emit light of different colors. The light-emitting element has a microcavity structure and intensifies light with a specific wavelength. The light-emitting elements that emit light of different colors each include a reflective layer and a conductive layer with a varied thickness over a lower electrode, and the lower electrode and the conductive layer are electrically connected to each other in the light-emitting element. The light-emitting elements with different colors being intensified by different optical path lengths are formed.Type: ApplicationFiled: November 24, 2021Publication date: January 4, 2024Inventors: Tomoya AOYAMA, Daiki NAKAMURA, Yutaka OKAZAKI
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Publication number: 20230230979Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
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Patent number: 11616085Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: GrantFiled: December 21, 2021Date of Patent: March 28, 2023Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
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Publication number: 20220416089Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.Type: ApplicationFiled: August 25, 2022Publication date: December 29, 2022Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
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Patent number: 11495691Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.Type: GrantFiled: May 27, 2019Date of Patent: November 8, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
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Publication number: 20220352387Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: ApplicationFiled: July 11, 2022Publication date: November 3, 2022Inventors: Yutaka OKAZAKI, Akihisa SHIMOMURA, Naoto YAMADE, Tomoya TAKESHITA, Tetsuhiro TANAKA
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Publication number: 20220293798Abstract: A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Yutaka OKAZAKI
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Patent number: 11393930Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.Type: GrantFiled: August 31, 2020Date of Patent: July 19, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Akihisa Shimomura, Naoto Yamade, Tomoya Takeshita, Tetsuhiro Tanaka
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Publication number: 20220199831Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: ApplicationFiled: February 3, 2022Publication date: June 23, 2022Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
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Publication number: 20220189996Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: ApplicationFiled: December 21, 2021Publication date: June 16, 2022Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Okazaki, Tomoaki MORIWAKA, Shinya SASAGAWA, Takashi OHTSUKI
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Patent number: 11245039Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: GrantFiled: April 9, 2019Date of Patent: February 8, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
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Patent number: 11211408Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.Type: GrantFiled: April 30, 2020Date of Patent: December 28, 2021Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
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Publication number: 20210242199Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.Type: ApplicationFiled: March 30, 2021Publication date: August 5, 2021Inventors: Tetsuhiro TANAKA, Yutaka OKAZAKI
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Publication number: 20210210640Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.Type: ApplicationFiled: May 27, 2019Publication date: July 8, 2021Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
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Patent number: 11024743Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: GrantFiled: April 9, 2019Date of Patent: June 1, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
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Patent number: 10971491Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.Type: GrantFiled: May 29, 2018Date of Patent: April 6, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuhiro Tanaka, Yutaka Okazaki