Patents by Inventor Yutaka Onishi

Yutaka Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8617911
    Abstract: The method includes the steps of preparing an epitaxial wafer by forming a multilayer semiconductor structure on a main surface of a substrate; forming stripe electrodes and bonding pads on the multilayer semiconductor structure with the bonding pads being respectively electrically connected to the stripe electrodes; forming a projection portion on the multilayer semiconductor structure; forming laser diode (LD) bars by cutting the epitaxial wafer; arranging the LD bars on a support surface such that a side surface thereof is oriented normal to the support surface, and disposing spacers between the LD bars; and forming a coating film on the side surface. The projection portion has a height, measured from the main surface of the substrate, greater than a height of the stripe electrodes. Furthermore, the laser diode bar has at least one projection portion.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: December 31, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Publication number: 20130330038
    Abstract: A coherent mixer includes a substrate including a principal surface, the principal surface having a first area and a second area; a multi-mode interference device provided on the first area of the substrate; a light-receiving device provided on the second area of the substrate, the light-receiving device including a plurality of waveguide-type photodiodes; a first input waveguide optically coupled to the multi-mode interference device; a second input waveguide optically coupled to the multi-mode interference device; a plurality of optical waveguides optically coupling the multi-mode interference device to the plurality of waveguide-type photodiodes; and a protective layer covering the first and second areas of the substrate, the protective layer covering the plurality of waveguide-type photodiodes. The protective layer has an opening in the first area of the substrate. In addition, the multi-mode interference device has a surface that is at least partially exposed at the opening of the protective layer.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 12, 2013
    Inventor: Yutaka ONISHI
  • Patent number: 8477820
    Abstract: A semiconductor laser device includes a first semiconductor stack portion that includes a grating layer and an active layer provided on the grating layer. The grating layer has a first region and second region; a diffraction grating provided in the first region; a semiconductor ridge structure portion provided on the first semiconductor stack portion and extending in a first direction; and a pair of first trenches provided along both side faces of the semiconductor ridge structure portion with the first region of the grating layer being located between the trenches. The first trenches penetrate through the grating layer. The first region of the grating layer has an end extending in a second direction intersecting with the first direction. The end of the first region of the grating layer reaches a trench.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: July 2, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 8389308
    Abstract: A method for producing a surface emitting semiconductor device includes a step of forming a semiconductor stacked structure including an active layer, a first semiconductor layer containing aluminum on the active layer, and a DBR portion, on the first semiconductor layer, to include alternating stacked second semiconductor layers and third semiconductor layers having different aluminum contents; a step of forming a mesa portion by etching the DBR portion and the first semiconductor layer; an oxidation step of oxidizing the first semiconductor layer from a side face of the mesa portion toward the inside of the mesa portion to form an annular oxidized region inside the first semiconductor layer; a first etching step of selectively etching an oxidized region formed in the DBR portion; and a second etching step of removing a peripheral portion of the DBR portion.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: March 5, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Publication number: 20120224820
    Abstract: A spot-size converter includes a cladding layer having a principal surface; a first core layer disposed on the principal surface and having a light input/output portion and a first transition portion having a width W1, the light input/output portion being coupled to the first transition portion and having a width that monotonously decreases in a first direction from the light input/output portion toward the first transition portion; and a second core layer disposed on the principal surface, the second core layer having a second transition portion and a propagation portion coupled to the second transition portion, the second transition portion having a width W2. The first core layer has a refractive index between refractive indices of the second core layer and the cladding layer. The first transition portion and the second transition portion are disposed with a gap therebetween and optically coupled to each other. A ratio (W1/W2) of the width W1 to the width W2 monotonously decreases in the first direction.
    Type: Application
    Filed: February 24, 2012
    Publication date: September 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yutaka ONISHI
  • Publication number: 20120214265
    Abstract: The method includes the steps of preparing an epitaxial wafer by forming a multilayer semiconductor structure on a main surface of a substrate; forming stripe electrodes and bonding pads on the multilayer semiconductor structure with the bonding pads being respectively electrically connected to the stripe electrodes; forming a projection portion on the multilayer semiconductor structure; forming laser diode (LD) bars by cutting the epitaxial wafer; arranging the LD bars on a support surface such that a side surface thereof is oriented normal to the support surface, and disposing spacers between the LD bars; and forming a coating film on the side surface. The projection portion has a height, measured from the main surface of the substrate, greater than a height of the stripe electrodes. Furthermore, the laser diode bar has at least one projection portion.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 23, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yutaka ONISHI
  • Patent number: 8218591
    Abstract: An LD with an improved heat dissipating function in the edge regions is disclosed. The LD provides the core region including the active layer and extending whole of the substrate, and the ridge waveguide structure on the core region that extends in a direction along which the light generated in the active layer is guided. The ridge waveguide structure is buried by a thick resin layer in both sides thereof, but the resin layer is removed in the edge regions close to respective facets of the LD.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: July 10, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaka Onishi, Hideki Yagi
  • Publication number: 20120094408
    Abstract: A method for producing a surface emitting semiconductor device includes a step of forming a semiconductor stacked structure including an active layer, a first semiconductor layer containing aluminum on the active layer, and a DBR portion, on the first semiconductor layer, to include alternating stacked second semiconductor layers and third semiconductor layers having different aluminum contents; a step of forming a mesa portion by etching the DBR portion and the first semiconductor layer; an oxidation step of oxidizing the first semiconductor layer from a side face of the mesa portion toward the inside of the mesa portion to form an annular oxidized region inside the first semiconductor layer; a first etching step of selectively etching an oxidized region formed in the DBR portion; and a second etching step of removing a peripheral portion of the DBR portion.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 19, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yutaka ONISHI
  • Publication number: 20120093190
    Abstract: A semiconductor laser device includes a first semiconductor stack portion that includes a grating layer and an active layer provided on the grating layer. The grating layer has a first region and second region; a diffraction grating provided in the first region; a semiconductor ridge structure portion provided on the first semiconductor stack portion and extending in a first direction; and a pair of first trenches provided along both side faces of the semiconductor ridge structure portion with the first region of the grating layer being located between the trenches. The first trenches penetrate through the grating layer. The first region of the grating layer has an end extending in a second direction intersecting with the first direction. The end of the first region of the grating layer reaches a trench.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 19, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Yutaka ONISHI
  • Publication number: 20110164642
    Abstract: An LD with an improved heat dissipating function in the edge regions is disclosed. The LD provides the core region including the active layer and extending whole of the substrate, and the ridge waveguide structure on the core region that extends in a direction along which the light generated in the active layer is guided. The ridge waveguide structure is buried by a thick resin layer in both sides thereof, but the resin layer is removed in the edge regions close to respective facets of the LD.
    Type: Application
    Filed: December 17, 2010
    Publication date: July 7, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yutaka ONISHI, Hideki Yagi
  • Patent number: 7953135
    Abstract: A vertical cavity surface emitting laser diode (VCSEL) is disclosed, which reduces the light scattering by the step formed at the interface between the dielectric DBR and the semiconductor that reflects the mesa shape of the tunnel junction. The dielectric DBR of the invention includes a plurality of first films with relatively smaller refractive index and a plurality of second films with relatively larger refractive index. These first and second films are alternately stacked to each other to cause the periodic structure of the refractive indices. The VCSEL of the invention, different from the conventional device, provides the dielectric film with relatively larger refractive index that directly comes in contact with the semiconductor to set the node of the optical standing wave at the interface between the dielectric DBR and the semiconductor.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: May 31, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 7852896
    Abstract: A VCSEL includes a GaAs substrate; a first semiconductor distributed Bragg reflector (DBR) disposed on the GaAs substrate and including a first part and a second part on the first part; a semiconductor mesa disposed on the first semiconductor DBR and including an active layer; and a second DBR on the semiconductor mesa. The first part is composed of an undoped semiconductor material. The second part includes third III-V compound semiconductor layers composed of a material containing indium and gallium as the group III element and phosphorus as the group V element and fourth III-V compound semiconductor layers composed of a material containing gallium as the group III element and arsenic as the group V element. The third III-V compound semiconductor layers and the fourth III-V compound semiconductor layers are doped with an n-type impurity.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaka Onishi, Hideyuki Doi
  • Patent number: 7852895
    Abstract: A VCSEL with a structure able to reduce the scattering within the optical cavity and its manufacturing method are disclosed. The VCSEL of the present invention provides, on the semiconductor substrate, the first DBR, the active layer, the p-type spacer layer, the heavily doped p-type mesa, the heavily doped n-type layer, the first n-type spacer and the second DBR in this order. The heavily doped n-type layer, which is formed so as to cover the p-type spacer layer and the heavily doped p-type mesa, forms the tunnel junction with respect to the heavily doped p-type mesa. Because the height, which is appeared in the surface of the n-type spacer layer, reflects the height of the heavily doped p-type mesa and is comparatively small, the light scattering between the second DBR and the n-type spacer layer is suppressed.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 7813403
    Abstract: A vertical cavity surface emitting laser diode (VCSEL) with a new structure is disclosed. The VCSEL of the invention provides the active layer, the first spacer layer, the tunnel junction, the second spacer layer burying the tunnel junction. Only the first spacer layer is ion-implanted to form a high-resistive region around the tunnel junction. The current injected into the second spacer layer is confined by the tunnel junction to reach the active layer, which reduces the increase of the parasitic resistance of the device. The high-resistive region around the tunnel junction reduces the parasitic capacitance of the device.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: October 12, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 7809041
    Abstract: In a surface emitting semiconductor laser, a first distributed Bragg reflector includes first and second semiconductor layers of a first conductive type. A second distributed Bragg reflector includes first and second portions. An active layer is provided on the first distributed Bragg reflector. The first distributed Bragg reflector, the active layer and the second distributed Bragg reflector are sequentially arranged in the direction of a predetermined axis. A III-V compound semiconductor region is provided on the first distributed Bragg reflector so as to surround the first portion of the second distributed Bragg reflector. A tunnel junction region with a mesa portion and a tunnel junction also is provided. Further, a second conductive type III-V compound semiconductor layer is provided between the active layer and the tunnel junction region.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: October 5, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 7738526
    Abstract: In a surface emitting semiconductor laser, the primary surface of a substrate includes first to third areas. The first and second areas are contiguous to each other, and the third area surrounds the first and second areas. A first DBR is provided on the substrate. An active layer is provided on the following: the first DBR; the first and second areas; and a boundary therebetween. A first semiconductor spacer layer is provided on the active layer. A second semiconductor spacer layer is provided on the first semiconductor spacer layer. The conductivity type of the first semiconductor spacer layer is different from that of the second semiconductor spacer layer. A tunnel junction region is on the first area and between the first and the second semiconductor spacer layers.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 15, 2010
    Assignee: Sumitomo Electric Industries Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 7668219
    Abstract: A surface emitting semiconductor device comprises: a semiconductor region including an active layer; a first DBR having first layers and second layers; and a second DBR. The first and second layers are alternately arranged, and the first layers are made of dielectric material. The first DBR, semiconductor region and second DBR are sequentially arranged along a predetermined axis, and the semiconductor region is provided between the first DBR and the second DBR. The cross section of the first DBR is taken along a reference plane perpendicular to the predetermined axis. The distance between two points on an edge of the cross section takes a first value in a direction of an X-axis of a two-dimensional XY orthogonal coordinate system defined on the reference plane, and the distance between two points on the edge takes a second value in a direction of a Y-axis of the above coordinate system. The first value is different from the second value.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: February 23, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Publication number: 20100014551
    Abstract: A VCSEL includes a GaAs substrate; a first semiconductor distributed Bragg reflector (DBR) disposed on the GaAs substrate and including a first part and a second part on the first part; a semiconductor mesa disposed on the first semiconductor DBR and including an active layer; and a second DBR on the semiconductor mesa. The first part is composed of an undoped semiconductor material. The second part includes third III-V compound semiconductor layers composed of a material containing indium and gallium as the group III element and phosphorus as the group V element and fourth III-V compound semiconductor layers composed of a material containing gallium as the group III element and arsenic as the group V element. The third III-V compound semiconductor layers and the fourth III-V compound semiconductor layers are doped with an n-type impurity.
    Type: Application
    Filed: May 8, 2009
    Publication date: January 21, 2010
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yutaka ONISHI, Hideyuki DOI
  • Publication number: 20090213892
    Abstract: A VCSEL with a structure able to reduce the scattering within the optical cavity and its manufacturing method are disclosed. The VCSEL of the present invention provides, on the semiconductor substrate, the first DBR, the active layer, the p-type spacer layer, the heavily doped p-type mesa, the heavily doped n-type layer, the first n-type spacer and the second DBR in this order. The heavily doped n-type layer, which is formed so as to cover the p-type spacer layer and the heavily doped p-type mesa, forms the tunnel junction with respect to the heavily doped p-type mesa. Because the height, which is appeared in the surface of the n-type spacer layer, reflects the height of the heavily doped p-type mesa and is comparatively small, the light scattering between the second DBR and the n-type spacer layer is suppressed.
    Type: Application
    Filed: February 25, 2009
    Publication date: August 27, 2009
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Yutaka Onishi
  • Patent number: 7569718
    Abstract: The invention enables reduction of catalyst in producing tetrafluorobenzonitrile by decyanation of one cyano group of tetrafluorodicyanobenzene by using a synthetic zeolite, particularly Zeolite 3A, 4A or 5A, in the reaction. Therefore, the invention provides an industrially useful process capable of producing tetrafluorobenzonitrile, a useful agrochemical and drug intermediate, by hydrogenolysis of tetrafluorodicyanobenzene to decyanate one cyano group with the use of catalyst in small amounts.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: August 4, 2009
    Assignee: Showa Denko K.K.
    Inventors: Toru Sasaki, Yutaka Onishi, Kohei Morikawa