Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.

Abstract: Provided is a liquid crystal display device (1) comprising a substrate (2), a base coating film (3) disposed on the substrate (2), a base insulating film (4) disposed on the base coating film (3), and a semiconductor film (20) disposed on the base insulating film (4) and made of a polysilicon film. Below the semiconductor film (20), a light-shielding film (28) is formed, which is embedded in the base coating film (3).

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.

Abstract: A semiconductor device (130) includes: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90) bonded to the bonding substrate (100), the semiconductor element (90) including semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body (50) facing the bonding substrate (100), and each of the underlying layers (51-54) including an insulating layer and a circuit pattern in the insulating layer, wherein an end of the semiconductor element (90) facing the thin film element (80) is provided in a stepped form so that the closer to the bonding substrate the underlying layers arc, the farther ends of the underlying layers facing the thin film element protrude, the end of the semiconductor element (90) is covered with a resin layer (120), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resin

Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.

Abstract: A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.

Abstract: A semiconductor device (130) including: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90a) bonded to the bonding substrate (100), the semiconductor element including a semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body facing the bonding substrate (100), wherein the underlying layer (54) closest to the bonding substrate (100) includes an extended section (E) formed by extending the circuit pattern toward the thin film element (80), a resin layer (120) is provided between the thin film element (80) and the semiconductor element (90a), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resin layer (120), the extended section (E), and the circuit patterns.

Abstract: A method of fabricating a semiconductor device of the present invention includes the steps of forming a single crystal semiconductor device, attaching the single crystal semiconductor device on a substrate, forming a TFT on a glass substrate, and electrically connecting the single crystal semiconductor device and the TFT. In the step of forming a single crystal semiconductor device, an alignment mark is provided at the single crystal semiconductor device. In the step of attaching a single crystal semiconductor device, the single crystal semiconductor device is positioned and attached on the glass substrate based on the machining accuracy of an attachment device. In the step of forming a TFT, the TFT is positioned and provided on the glass substrate based on the alignment mark provided at the single crystal semiconductor device.

Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.

Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.

Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure.

Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.

Abstract: A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded.

Abstract: An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types of nano wire element. With this, it is possible to dramatically improve a function of the integrated circuit device, as compared with an integrated circuit device including a substrate on which one type of nano wire element is provided.

Abstract: Disclosed is a glass substrate (20) that is capable of constituting a semiconductor device (10) when a monocrystalline silicon thin film (90) is provided on the surface of the substrate by transfer. The surface of the glass substrate (20) has a receiving surface (22) onto which the monocrystalline silicon thin film (90) can be provided. The height of the ripples on the receiving surface (22) having a period of 200 to 500 microns is no more than 0.40 nm.

Abstract: A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed.

Abstract: A semiconductor device of the present invention is arranged in such a manner that a MOS non-single-crystal silicon thin-film transistor including a non-single-crystal silicon thin film made of polycrystalline silicon, a MOS single-crystal silicon thin-film transistor including a single-crystal silicon thin film, and a metal wiring are provided on an insulating substrate. With this arrangement, (i) a semiconductor device in which a non-single-crystal silicon thin film and a single-crystal silicon thin-film device are formed and high-performance systems are integrated, (ii) a method of manufacturing the semiconductor device, and (iii) a single-crystal silicon substrate for forming the single-crystal silicon thin-film device of the semiconductor device are obtained.

Abstract: Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).

Abstract: This invention provides a semiconductor device having a semiconductor element that has low-resistance and a stable contact connection, even when the wiring is connected from the side of the single-crystal silicon layer on which the impurity concentration is lower. This invention provides a semiconductor device comprising, on a substrate, a semiconductor device having a single-crystal semiconductor film and a wiring connected to the single-crystal semiconductor film, and in the single-crystal semiconductor film, an impurity concentration on one surface side is different from an impurity concentration on another surface side, the wiring being connected to the surface side on which the impurity concentration is lower, the resistivity of a region of the single-crystal semiconductor film to which the wiring is connected being no less than 1 ??cm and no more than 0.01 ?cm.