Patents by Inventor Yutaka Tamiya

Yutaka Tamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190205487
    Abstract: An information processing apparatus includes a memory; and a processor coupled to the memory and the processor that creates module partitioning candidates of a plurality of software codes including one or more input nodes from a plurality of input nodes in a data flow graph and calculates a cost corresponding to a bit width of a signal line of the module partitioning candidates for each of the created plurality of module partitioning candidates, and selects one or more module partitioning candidates having a given cost from the plurality of module partitioning candidates as a partitioning target module based on the calculated cost.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 4, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Yutaka TAMIYA
  • Publication number: 20190079800
    Abstract: An apparatus identifies each of one or more strongly connected graphs included in a control flow graph of a program, and calculates a characteristic value indicating a characteristic of a first process indicated by the identified strongly connected graph, based on profile information indicating a characteristic of a second process indicated by each of one or more nodes included in the control flow graph. The apparatus determines, based on the calculated characteristic value of the first process and a requirement set for an accelerator, whether or not the first process is executable by the accelerator.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Publication number: 20190042421
    Abstract: A memory control apparatus including at least one buffer memory and a processor coupled to the at least one buffer memory, and the processor configured to execute a process including receiving pieces of data to be written to a memory device, each of the pieces of data being associated with an index indicating a position of memory region of in the memory device, storing the pieces of data to the at least one buffer memory, sorting the pieces of data stored in the at least one buffer memory in accordance with the index, write the pieces of data sorted in the at least one buffer memory to the memory device at once, by using a block access function that writes plural pieces of data each of which the position indicated by the index is included in the predetermined index range.
    Type: Application
    Filed: October 10, 2018
    Publication date: February 7, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Publication number: 20190042271
    Abstract: An apparatus includes an arithmetic circuit that performs a pipeline operation on first data as an input; and a determination circuit that determines, based on pipeline operation results, whether to perform the pipeline operation by inputting, to the arithmetic circuit, second data different from the first data, wherein when the determination circuit has determined that the pipeline operation is to be performed by inputting the second data to the arithmetic circuit, the arithmetic circuit suspends the pipeline operation using the second data thereof, and performs the pipeline operation with the first data input until the second data is input, and when the second data is input, the arithmetic circuit resumes the pipeline operation using the second data.
    Type: Application
    Filed: July 27, 2018
    Publication date: February 7, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Patent number: 10024911
    Abstract: A memory unit stores first and second code values calculated by encoding a first sequence, contained in a first word, and a remaining second sequence of a target sequence, and the number of bytes from a word start to a target sequence start. A code value calculating unit calculates a code value for each byte, based on signal sequence. A first sequence detecting unit detects the first sequence, by comparing the first code value with a difference between the code values at the last byte of a word and at the byte corresponding to the number of bytes. An expected value calculating unit calculates an expected code value at the target sequence end, based on the code value at detection of the first sequence and the second code value. A determination unit signals that the target sequence is detected, when the code value equals the expected value.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: July 17, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Patent number: 9857423
    Abstract: A debugging circuit including: a storage configured to store a first code value which is calculated by an encoding method in which a value is changed according to a sequence of a signal in a debugging target circuit, and indicates a stop condition of the debugging target circuit; a code value calculator configured to calculate a second code value by the encoding method based on the signal each time when the signal is changed; and an operation stopper configured to stop an operation of the debugging target circuit when the first code value and the second code value are identical to each other.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: January 2, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Patent number: 9753084
    Abstract: A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 5, 2017
    Assignee: FUJITSU LIMTIED
    Inventor: Yutaka Tamiya
  • Patent number: 9720037
    Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshiyuki Ichiba, Yoshinori Tomita, Yutaka Tamiya
  • Patent number: 9602095
    Abstract: In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, an intermediate register is disposed between the first register and the second register. A first selection circuit between the first register and the intermediate register and a second selection circuit between the intermediate register and the second register are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit. The value of L for minimizing the circuit amount is calculated based on values of the M and the N. Therefore, it is possible to reduce the circuit amount of the multiplexer circuit capable of performing data access with respect to large-volume data.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: March 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Publication number: 20160327610
    Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.
    Type: Application
    Filed: March 30, 2016
    Publication date: November 10, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Toshiyuki ICHIBA, Yoshinori Tomita, Yutaka Tamiya
  • Publication number: 20160282413
    Abstract: A memory unit stores first and second code values calculated by encoding a first sequence, contained in a first word, and a remaining second sequence of a target sequence, and the number of bytes from a word start to a target sequence start. A code value calculating unit calculates a code value for each byte, based on signal sequence. A first sequence detecting unit detects the first sequence, by comparing the first code value with a difference between the code values at the last byte of a word and at the byte corresponding to the number of bytes. An expected value calculating unit calculates an expected code value at the target sequence end, based on the code value at detection of the first sequence and the second code value. A determination unit signals that the target sequence is detected, when the code value equals the expected value.
    Type: Application
    Filed: February 9, 2016
    Publication date: September 29, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Yutaka TAMIYA
  • Patent number: 9339205
    Abstract: A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 17, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yutaka Tamiya, Hiroaki Iwashita, Hiroyuki Higuchi
  • Publication number: 20160084906
    Abstract: A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match.
    Type: Application
    Filed: June 26, 2015
    Publication date: March 24, 2016
    Inventor: Yutaka Tamiya
  • Publication number: 20160054388
    Abstract: A debugging circuit including: a storage configured to store a first code value which is calculated by an encoding method in which a value is changed according to a sequence of a signal in a debugging target circuit, and indicates a stop condition of the debugging target circuit; a code value calculator configured to calculate a second code value by the encoding method based on the signal each time when the signal is changed; and an operation stopper configured to stop an operation of the debugging target circuit when the first code value and the second code value are identical to each other.
    Type: Application
    Filed: May 28, 2015
    Publication date: February 25, 2016
    Inventor: Yutaka Tamiya
  • Publication number: 20150236684
    Abstract: In a multiplexer circuit which loads N data segments (N is an integer of N<M) led by an arbitrary data segment from a first register storing M data segments (M is an integer equal to or larger than two) to a second register, an intermediate register is disposed between the first register and the second register. A first selection circuit between the first register and the intermediate register and a second selection circuit between the intermediate register and the second register are designed based on a value of L for minimizing a circuit amount of the first selection circuit and the second selection circuit. The value of L for minimizing the circuit amount is calculated based on values of the M and the N. Therefore, it is possible to reduce the circuit amount of the multiplexer circuit capable of performing data access with respect to large-volume data.
    Type: Application
    Filed: January 26, 2015
    Publication date: August 20, 2015
    Inventor: Yutaka Tamiya
  • Patent number: 8949019
    Abstract: A communication device includes a memory and a processor coupled to the memory. The processor executes a process including calculating an amount of electricity available in a second device while a first communication unit and a second communication unit with each other, determining a first generation unit to be a generation unit, when the amount of electricity thus calculated is smaller than a predetermined amount, out of the first generation unit that generates navigation information based on information acquired by an information acquisition unit and a second generation unit, and controlling the second device so as to stop supplying power to the second generation unit and to output the navigation information generated by the first generation unit when the first generation unit is determined.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Fujitsu Limited
    Inventors: David Thach, Atsushi Ike, Yutaka Tamiya, Ryosuke Oishi
  • Patent number: 8832636
    Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Limited
    Inventors: Ryosuke Oishi, David Thach, Yutaka Tamiya
  • Publication number: 20140115555
    Abstract: A non-transitory, computer-readable recording medium stores therein a verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition>the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in
    Type: Application
    Filed: December 23, 2013
    Publication date: April 24, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Ryosuke OISHI, David Thach, Yutaka TAMIYA
  • Patent number: 8671372
    Abstract: A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventors: Ryosuke Oishi, David Thach, Yutaka Tamiya
  • Patent number: 8621295
    Abstract: A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: December 31, 2013
    Assignee: Fujitsu Limited
    Inventor: Yutaka Tamiya