Patents by Inventor Yuuji Hinatsu

Yuuji Hinatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080237646
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Application
    Filed: May 29, 2008
    Publication date: October 2, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
  • Patent number: 7394156
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: July 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
  • Patent number: 7170115
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
  • Publication number: 20050127406
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Application
    Filed: January 25, 2005
    Publication date: June 16, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
  • Publication number: 20020043668
    Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.
    Type: Application
    Filed: October 5, 2001
    Publication date: April 18, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu