Patents by Inventor Yuuji Shirai

Yuuji Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5365402
    Abstract: A cooling apparatus for an electronic device of high calorific density including an elastomer interposed between a semiconductor chip and a heat sink so as to connect them thermally. The elastomer may also be in close contact with a large number of semiconductor chips having various configurations which are mounted on a board, so that the elastomer is thermally connected with them, whereby the elastomer absorbs thermal deformations.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: November 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Hatada, Shigeo Ohashi, Tadakatsu Nakajima, Heikichi Kuwahara, Hitoshi Matsushima, Motohiro Sato, Hiroshi Inouye, Takao Ohba, Akira Yamagiwa, Kanji Otsuka, Yuuji Shirai
  • Patent number: 5304844
    Abstract: A semiconductor device is provided having a semiconductor pellet that is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base. External terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, as well as inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: April 19, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Osamu Horiuchi, Gen Murakami, Hiromichi Suzuki, Hajime Hasebe, Kanji Otsuka, Yuuji Shirai, Takayuki Okinaga, Takashi Emata
  • Patent number: 5067007
    Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: November 19, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kanji Otsuka, Masao Kato, Takashi Kumagai, Mitsuo Usami, Shigeo Kuroda, Kunizo Sahara, Takeo Yamada, Seiji Miyamoto, Yuuji Shirai, Takayuki Okinaga, Kazutoshi Kubo, Hiroshi Tachi, Masayuki Kawashima
  • Patent number: 5032895
    Abstract: A semiconductor device comprising the fact that a semiconductor pellet is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base, and that external terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, and inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: July 16, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Osamu Horiuchi, Gen Murakami, Hiromichi Suzuki, Hajime Hasebe, Kanji Otsuka, Yuuji Shirai, Takayuki Okinaga, Takashi Emata
  • Patent number: 5018004
    Abstract: A semiconductor chip package technology which uses thin film wiring from the chip to the package terminals for increased line density and decreased parasitic capacitance and uses a thin film adhesion layer for improved heat conductivity between the package substrate and its sealing cap. The package uses a thin conductor film deposited along the element mounting surface of a sintered substrate. An adhesion layer, to provide a high quality bond between the sealing cap and substrate, is then deposited on the substrate peripheral area by successively laminating metal and metallized layers, or by depositing a single layer of low metal glass. The adhesion layer is thinner and of larger area than thick film technology, for improved heat conduction.
    Type: Grant
    Filed: November 28, 1989
    Date of Patent: May 21, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Shouji Matsugami, Yuuji Shirai, Kanji Otsuka, Hiroshi Koguma, Takashi Emata