Abstract: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.

Abstract: A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time.

Abstract: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.

Abstract: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.

Abstract: A relay apparatus, terminal apparatus and relay method for relaying signals with a reduced scale of the apparatus, without temporally switching between transmission and reception and with reduced waste of time when relay is performed at the same frequency on a radio communication network on which bidirectional communication is performed. A radio reception section 202 outputs information signals to a switch 208, outputs relay control signals to a demodulation section 204 after subjecting predetermined radio reception processing. The demodulation section 204 demodulates a relay control signal. A relay control signal processing section 206 decides the possibility of relay of information signals and inquires, when the relay is possible, whether the terminal apparatus on the receiving side can receive this information signal or not. Furthermore, the relay control signal processing section 206 connects a switch 208 during the stored relay time.

Abstract: An A/D conversion section (101) performs oversampling on an analog signal at a rate M times the symbol rate to convert into digital signals. A FIR filtering section (102) has two delay-element sequences each with a plurality of delay elements, and the two sequences have different delay directions of input signal, i.e., forward direction and reverse direction. The delay directions of input signal can be switched, and according to the finite impulse response train having such delay-element sequences, convolutional calculation is performed. A phase determining section (103) determines a phase used in making a decision in a decision section (104). The decision section (104) makes a decision on a filtered signal using the phase determined in the phase determining section (103) to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with high accuracy without increasing the oversampling number, and performs fast calculation while having a reduced circuitry scale.

Abstract: Wiring is variably connected between delay section 102 having N delay elements, D0 to DN-1, and multiplying section 104 having N multipliers, c(0) to c(N-1). Further, wiring is variably connected between multiplying section 104 and adding section 106 having N adders, K0 to KN-1. When the oversampling number of an input signal is dynamically varied, wiring control section 109 varies the wiring so as to obtain a filter structure with a number of parallels corresponding to the oversampling number. Thus, the finite impulse response filter is capable of responding to the dynamically varied oversampling number, and reducing its circuit size.

Abstract: A receiving ckt for receiving a transmitted SIG including FRQ divided carriers, comprises: a FRQ conversion ckt responsive to the LO SIG with a LO for generating a LO SIG with LO FRQ controlled according to a FRQ CONT SIG for FRQ converting the transmitted SIG into an IF SIG; a orthogonal signal separation ckt separating the IF SIG into I and Q components; a complex FFT conversion ckt for complex FFT converting the I and Q components and outputting conversion SIGs to be decoded arranged in FRQ base; an ELEC PWR measurement ckt measuring values of ELEC PWRs of the conversion SIGs; and a prediction ckt for predicting a CTR FRQ of the FRQ divided carriers from a FRQ distribution of the values of ELEC PWRs from the ELEC PWR measurement ckt and generating the FRQ CONT SIG according to the predicted center FRQ. The CTR FRQ may be detected by a REF carrier detection ckt responsive to the complex FFT processing ckt detecting a REF carrier or a carrier pattern included in the transmitted SIG.

Abstract: A timing signal generator includes a demodulator for an input modulated signal to provide first and second baseband signals having a quadrature relation relative to each other. A converter is used to convert the first and second baseband signals into angle data representing a phase, and a calculator is used to calculate a difference between the phase represented by current angle data and the phase represented by previous angle data, preceding the current angle data by a 1-symbol interval. The calculator outputs data representative of the calculated phase difference. A further converter converts the calculator output data into a binary reference signal responsive to which of predetermined divided regions contains a point corresponding to the calculated difference data. Also included is a generator for generating a symbol timing signal in synchronism with the binary reference signal.

Abstract: In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals.

Abstract: A complex angle converter includes a comparing device. The comparing device operates to derive first difference data representing a difference between predetermined reference data and data represented by a first baseband signal. The comparing device further operates to derive second difference data representing a difference between the predetermined reference data and data represented by a second baseband signal having a quadrature relation with the first baseband signal. The comparing device further operates for comparing absolute values of the first difference data and the second difference data, and for outputting a signal representative of a result of the comparing. The complex angle converter also includes a device serving to group an inversion of a highest bit of the first baseband signal and second highest and lower bits of the second baseband signal into a first set.

Abstract: In a frame synchronizing apparatus for a receiver apparatus of a digital data radio communications system in which data are transmitted in frame periods with a fixed data sequence contained each frame, a data correlation circuit obtains successive sequences of values of vector difference between vector values constituting a demodulated digital baseband signal, and successively compares these sequences with a fixed vector difference sequence corresponding to the fixed data sequence, to derive a correlation signal substantially unaffected by any phase rotation in the baseband signal. A frame synchronizing circuit formed as a PLL for generating a frame synchronizing signal, includes a phase comparator which periodically indicates whether a detected phase difference between the correlation signal and frame synchronizing signal is effectively zero, positive or negative, and a counter holding a count value indicating a cumulative phase error between these signals.

Abstract: A quadrature demodulator includes a device for generating first and second reference signals having a quadrature relation with each other. A first demodulating device serves to compare phases of the first reference signal and an input modulated signal to demodulate the input modulated signal into a first binary baseband signal. A second demodulating device serves to compare phases of the second reference signal and the input modulated signal to demodulate the input modulated signal into a second binary baseband signal having a quadrature relation with the first baseband signal. A first counting device operates to count pulses of a clock signal in response to the first baseband signal. A second counting device operates to count pulses of the clock signal in response to the second baseband signal. An address signal is generated in response to the output signals of the first and second counting devices.

Abstract: A diversity receiver includes a first antenna and a second antenna. A first receiving section connected to the first antenna serves to convert a digital modulation wave induced at the first antenna into a first intermediate-frequency signal. A first band pass filter connected to the first receiving section serves to subject the first intermediate-frequency signal to a band pass filtering process. A second receiving section connected to the second antenna serves to convert a digital modulation wave induced at the second antenna into a second intermediate-frequency signal. A second band pass filter connected to the second receiving section serves to subject the second intermediate-frequency signal to a band pass filtering process. A switch alternately selects one of output signals of the first and second band pass filters at a period equal to a half of a period corresponding to the symbol rate.

Abstract: A terminal unit apparatus for a time division multiplexing access radio communications system formed of a base station and a number of terminal units remote from the base station, includes a 2-dimensional adaptive equalizer circuit for equalizing two quadrature-relationship baseband signals which are obtained from a received quadrature digital modulation signal during receiving operation of the terminal unit, and an internal signal source which generates a local oscillator signal for use in demodulating a received signal to obtain these baseband signals. A frequency correction quantity is derived from the average rate of variation in each symbol interval of the ratio of the two main tap coefficients of the 2-dimensional adaptive equalizer circuit, and used to correct the frequency of operation of the internal signal source during both receiving operation and also in transmitting operation, in which the internal signal source provides a carrier signal for modulation.