Patents by Inventor Yuzi Kanazawa

Yuzi Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200292509
    Abstract: When chromatogram data for a target sample have been acquired, a peak position estimator determines an estimated result of the position of the starting and/or ending point of a peak as well as the confidence value representing the reliability of the estimation, using a trained model stored in the trained model storage section. Normally, a plurality of estimated results of the starting point and/or ending point of the peak are acquired for one peak. A peak information correction processor identifies a candidate having the highest confidence as a prime candidate, and superposes a plurality of candidates including the prime candidate, with their respective confidence values, on a displayed chromatogram. An operator referring to the confidence values selects a peak which needs close checking or correction, and corrects the starting point and/or ending point of the selected peak, for example, by selecting and indicating a candidate other than the prime candidate.
    Type: Application
    Filed: November 9, 2017
    Publication date: September 17, 2020
    Applicant: SHIMADZU CORPORATION
    Inventors: Takeshi OSOEKAWA, Yusuke HIDA, Yuzi KANAZAWA, Shinji KANAZAWA, Yohei YAMADA, Hiroyuki YASUDA, Akihiro KUNISAWA
  • Publication number: 20200279408
    Abstract: A model constructed by a training process using the technique of deep learning using the training data including images created from a large number of chromatograms and correct peak information is previously stored in a trained model storage section. When chromatogram data for a target sample acquired with an LC measurement unit are inputted, an image creator converts the chromatogram into an image and creates an input image in which one of the two areas divided by the chromatogram curve as the boundary in the image is filled. A peak position estimator inputs the pixel values of the input image into a trained model using a neural network, and obtains the position information of the starting point and/or ending point of the peak and a peak detection confidence as the output. A peak determiner determines the starting point and/or ending point of each peak based on the peak detection confidence.
    Type: Application
    Filed: November 9, 2017
    Publication date: September 3, 2020
    Applicant: SHIMADZU CORPORATION
    Inventors: Takeshi OSOEKAWA, Yusuke HIDA, Yuzi KANAZAWA, Shinji KANAZAWA, Yohei YAMADA, Hiroyuki YASUDA, Akihiro KUNISAWA, Hidetoshi TERADA
  • Publication number: 20200193329
    Abstract: A computer-implemented learning method includes inputting a plurality of pieces of input data and labels representing the plurality of pieces of input data into an encoder configured to output context variables associated with each of the plurality of pieces of input data, inputting the plurality of pieces of input data and the context variables output by the encoder into a decoder configured to output decision labels associated with the plurality of pieces of input data respectively, and learning parameters of the encoder and the decoder so that each of the decision labels matches with a corresponding label of the labels representing the plurality of the plurality of pieces of input data.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 18, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi OSOEKAWA, TAKASHI KATOH, Yusuke Hida, Yuzi KANAZAWA
  • Patent number: 9348958
    Abstract: A disclosed method includes: converting, for each sample point, a set of performance item values for a sample point into coordinate values of a mesh element containing the set among plural mesh elements obtained by dividing a space mapped by the performance items; generating a binary decision graph representing a group of the coordinate values of the sample points; calculating the number of sample points including second sample points that dominates a first sample point and the first sample point, by counting the number of paths in the binary decision graph from a root node to a leaf node representing “1” through at least one of certain nodes corresponding to coordinate values that are equal to or less than coordinate values of the first sample point; and calculating a yield of the first sample point by dividing the calculated number by the number of the plural sample points.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: May 24, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroyuki Higuchi, Yu Liu, Yuzi Kanazawa
  • Patent number: 8726100
    Abstract: Among the combinations of failure candidates which combinations are generated by a generator, one combination that minimizes a cost derived in a cost calculator is selected. For the selected combination of failure candidates, a function, which specifically provides a correlation between one or more failure factor and an error (or error rate) of each failure element is output. A correct failure factor is estimated on the basis of the function.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Patent number: 8539324
    Abstract: A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: September 17, 2013
    Assignee: Fujitsu Limited
    Inventors: Tsutomu Ishida, Yuzi Kanazawa
  • Publication number: 20130104009
    Abstract: A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit.
    Type: Application
    Filed: August 28, 2012
    Publication date: April 25, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tsutomu Ishida, Yuzi Kanazawa
  • Patent number: 8407642
    Abstract: A leak current calculation apparatus includes an acquiring section for acquiring partial circuit information, and a grouping section for forming a plurality of groups each comprising a part of the partial circuits connected with each other and for generating group information. The apparatus includes a leak difference value calculating section for calculating a leak difference value, which is a difference between a provisional maximum value acquired by adding up the maximum values of the leak current values of all the partial circuits and a sum of maximum values of the leak current values contained in the group information of the groups, and a maximum leak current calculating section for calculating the maximum leak current value of the integrated circuit by adjusting the provisional maximum value with the leak difference value.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 26, 2013
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Publication number: 20130046728
    Abstract: A disclosed method includes: converting, for each sample point, a set of performance item values for a sample point into coordinate values of a mesh element containing the set among plural mesh elements obtained by dividing a space mapped by the performance items; generating a binary decision graph representing a group of the coordinate values of the sample points; calculating the number of sample points including second sample points that dominates a first sample point and the first sample point, by counting the number of paths in the binary decision graph from a root node to a leaf node representing “1” through at least one of certain nodes corresponding to coordinate values that are equal to or less than coordinate values of the first sample point; and calculating a yield of the first sample point by dividing the calculated number by the number of the plural sample points.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki HIGUCHI, Yu Liu, Yuzi Kanazawa
  • Publication number: 20120204063
    Abstract: Among the combinations of failure candidates which combinations are generated by a generator, one combination that minimizes a cost derived in a cost calculator is selected. For the selected combination of failure candidates, a function, which specifically provides a correlation between one or more failure factor and an error (or error rate) of each failure element is output. A correct failure factor is estimated on the basis of the function.
    Type: Application
    Filed: December 12, 2011
    Publication date: August 9, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Yuzi KANAZAWA
  • Patent number: 8181136
    Abstract: In order to confirm a propagation range of a signal whose signal value is fixed by a control signal to restrain switchings is within a predetermined range, it is judged by results of the logic simulation whether or not a switching restraining mode is enabled. If it is enabled, a switching probability restraint information list including the detected time and an ID of the net whose signal value is fixed is set to the net whose signal value is fixed, and then is propagated to the next net according to the results of the logic simulation. If the circuit changes are appropriated conducted, the results of the logic simulation do not satisfy the propagation condition of the switching probability restraint information list. Accordingly, the switching probability restraint information list is not propagated over the predetermined range, and no problem is detected.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Patent number: 8151367
    Abstract: An information processing system includes a management apparatus having a transmission preventing part preventing transmission of a predetermined usage allowing signal allowing usage of a predetermined device, in response to receiving a predetermined usage preventing instruction for the predetermined device.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: April 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Yuzi Kanazawa, Yoshihiro Tsuchiya
  • Patent number: 8074192
    Abstract: The circuit volume of a system under design is reduced by a circuit conversion involving consolidation (sharing) of common parts in the system by a representative part. The design data of the system post-conversion is used to verify operation of the system. However, the verification results for the system post-conversion express signals (e.g., signal X) of plural modules (e.g., modules a to c) as one signal waveform thereby making debugging difficult when a bug is found. Given this situation, from the verification results of the system post-conversion, signal-generation-use data is generated for generating the signal waveforms (here, respective signal waveforms for the modules a to c) of the system before conversion. After verification is complete, a signal waveform for each of the modules a to c is generated using the verification results for the system under design and the signal-generation-use data.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: December 6, 2011
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Patent number: 8024684
    Abstract: Design data of a cell group is copied to obtain design data of an antecedent cell group and of a subsequent cell group. Design data of a combinational circuit is copied to generate the combinational circuits in plural corresponding to a given number of cycles n (n=2, 3, 4 . . . , where n=3 in FIG. 4). The design data of the combinational circuits are connected in series between the design data of the antecedent cell group and the design data of the subsequent cell group. As a result, design data of an input constraint circuit representing an input constraint(s) of the circuit can be generated.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: September 20, 2011
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Patent number: 7966590
    Abstract: A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: June 21, 2011
    Assignee: Fujitsu Limited
    Inventors: Yuzi Kanazawa, Takahide Yoshikawa, Tsuneo Nakata
  • Publication number: 20110088004
    Abstract: A method includes generating Atool(j, i) representing an effect of a tool j for a chip i by using outputs from M kinds of tools that carries out a processing for design support for layout data of N kinds of chips; calculating a difference ?(i) between an actual parameter value of the chip i, which is stored in an actual value storage storing, for each chip, the actual parameter value, and an estimated parameter value of the chip i, which is an estimated value of the parameter value calculated from data for the chip i and stored in an estimated value storage storing, for each chip, the parameter estimate value, and calculating, for each chips i, an influence degree Xtool(j) of each tool j, which satisfies ?(i)=?Atool(j, i)*Xtool(j); and identifying a tool j whose influence degree Xtool(j) is largest.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 14, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Yuzi Kanazawa
  • Publication number: 20100237878
    Abstract: A leak current calculation apparatus includes an acquiring section for acquiring partial circuit information, and a grouping section for forming a plurality of groups each comprising a part of the partial circuits connected with each other and for generating group information. The apparatus includes a leak difference value calculating section for calculating a leak difference value, which is a difference between a provisional maximum value acquired by adding up the maximum values of the leak current values of all the partial circuits and a sum of maximum values of the leak current values contained in the group information of the groups, and a maximum leak current calculating section for calculating the maximum leak current value of the integrated circuit by adjusting the provisional maximum value with the leak difference value.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 23, 2010
    Applicant: Fujitsu Limited
    Inventor: Yuzi KANAZAWA
  • Patent number: 7631280
    Abstract: In manufacturing a structured ASIC, after production of an intermediate product with a transistor layer or the transistor layer and a metal layer, the transistor speed of each intermediate product is measured and, using the speed and associated statistical data, a maximum transistor speed delay is estimated. Based on the estimate, the type of the structured ASIC is determined from among an existing list of LSI circuit types.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: December 8, 2009
    Assignee: Fujitsu Limited
    Inventor: Yuzi Kanazawa
  • Publication number: 20090300564
    Abstract: In order to confirm a propagation range of a signal whose signal value is fixed by a control signal to restrain switchings is within a predetermined range, it is judged by results of the logic simulation whether or not a switching restraining mode is enabled. If it is enabled, a switching probability restraint information list including the detected time and an ID of the net whose signal value is fixed is set to the net whose signal value is fixed, and then is propagated to the next net according to the results of the logic simulation. If the circuit changes are appropriated conducted, the results of the logic simulation do not satisfy the propagation condition of the switching probability restraint information list. Accordingly, the switching probability restraint information list is not propagated over the predetermined range, and no problem is detected.
    Type: Application
    Filed: January 22, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Yuzi Kanazawa
  • Publication number: 20090234620
    Abstract: The circuit volume of a large-scale system under design is reduced by a circuit conversion involving the sharing of common parts in the system. Thus, even large-scale systems can be mounted on hardware, such as a field programmable gate array, enabling a reduction in verification time. Further, as the waveform of each signal can be referenced as verification results, efficient debugging by the user can be facilitated.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 17, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Yuzi Kanazawa