Abstract: A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation.

Abstract: In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.

Abstract: A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

Abstract: An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

Abstract: A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.

Abstract: An analog-to-digital converter includes a capacitor array circuit for determining m upper bits of a digital output, which includes a plurality of capacitors having binary-weighted capacitance ratios and a plurality of switches and which is connected to an input terminal of a sampled analog voltage and a reference voltage source. A resistor string circuit is provided for determining n lower bits of the digital output, including a plurality of switches and which is connected to the capacitor array circuit. A voltage comparator compares an output voltage of the capacitor array circuit with the ground potential and successive approximation registers successively provide pulses for controlling the switches of the capacitor array circuit and the resistor string circuit in accordance with the output of the voltage comparator. A circuit generates timing pulses for controlling the operation of the successive approximation registers. The resistor string circuit applies voltages equal to i/2.sup.

Abstract: In a memory array of memory cells each having at least a gate, a substrate, a source and a drain, a writing operation is effected when the substrate and the source and drain are at the same potential and when a potential difference V.sub.p exists between the potential of the substrate and the source and drain and that at the gate. The stored contents are erased when a potential difference V.sub.p exists between the gate and the substrate. The stored condition is prevented from changing when a potential difference V.sub.p exists between the substrate and the gate and when a potential difference V.sub.wd exists between the substrate and the source and drain. When such a memory array is partially erased, cells not to be erased are sequentially driven by applying a voltage V.sub.wd between the source and drain and the substrate of the cell, applying a voltage V.sub.p between the gate and the substrate of the cell, and applying the same potential to the substrate and the gate of the cell.

Abstract: A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the binary counter and which is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs of the logical array in response to the clock pulses from the clock source with the outputs of the flip-flop circuits being used as timing signals.

Abstract: In a memory device which has a plurality of recirculating type storage loops and in which information of the same addresses of the respective storage loops can be read and written in parallel, a memory device wherein information representing whether or not the corresponding storage loop is a bad or defective loop is written in a specified address of each of the storage loops.

Abstract: In a system comprising a memory, an input/output control device, a direct memory access controller and a data bus, the transfer of data between the memory and the input/output control device via the data bus by means of said direct memory access controller during the period of direct memory access mode is effected by controlling the data transfer direction on a data bus so that a control signal for determining the direction of transferring the data by said data bus is recognized in an inverted manner at the memory or the input/output control device only during the period of a data transfer cycle in the direct memory access mode.

Abstract: A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diod

Abstract: A data processing system comprises first and second arithmetic units for processing emergent tasks and non-emergent tasks, respectively, a memory for storing the data from the arithmetic units, and a control unit. The control unit selects either an interrupt task or a task being processed in response to the priority levels of the tasks. The first or second arithmetic unit is operated in response to whether a selected task is an emergent task or a non-emergent task.

Abstract: Interrupt signals are set into interrupt level memory registers each of which is provided for each interrupt level, and an interrupt receiving register having a number of bits equal to the number of interrupt level memory registers is disposed within an LSI computer. Transmission of interrupt information from the interrupt level memory registers to the receiving register is effected through a single interface line in synchronism with clock pulses.