Abstract: A memory interface mechanism is driven from the memory controller side which comprises lines which are shared by the memory user devices and lines which are specific to the memory user devices. The shared lines are the address and data bus lines the byte select lines, the data and address clock lines and the last operation line. The specific lines are the request lines, the address user indicator lines and data user indicator lines. A user initiates a memory operation by activating its request line and then waits for the activation by the memory interface control circuit for the activation of the address and data user indicator lines. The user controls the address and data transfer count and ends the transfer by activating the last operation line. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven which allows full advantage to be taken of a page mode facility of the memory.

Abstract: Disclosed is a memory access control device for a memory organized in 2.sup.n byte words and having the capability of addressing each byte in a word under control of byte select signals (BS), through an m-byte wide bus 22, with 2.sup.n /m being an integer k, to write or read data byte bursts comprising a variable count of bytes. For writing, k sets of m bytes received from bus 22 are stored into 2.sup.n registers 40 during each bus period T; they are then transferred into buffer 30 which comprises successive location of 2.sup.n bytes positions, through an alignment and control logic 42, which causes the buffer to be written in such a way that it maps the data arrangement in memory. This depends upon the least significant bits of the memory starting address determining the byte location within the memory words. Once the complete data burst is written into the buffer, the buffer content is transferred to the memory.

Abstract: An interface mechanism is described for controlling the exchange of information between two devices, such as a direct memory access controller 12 and adapter 5 through bus 10. The exchange is initiated by the adapter which activates the request line 44 and read/write signal on line 62 indicating whether a memory read or write operation is requested. The controller sends back a grant signal on line 46 when the request may be serviced. Ready line 60 is monitored and checked by the adapter and valid line 52 is monitored and checked by the controller. Turn around signal on line 64 controls the direction of the transfer on bidirectional data lines 66. A write or read operation begins with the transmission by the adapter of control parameters (address and byte count). Then for a write operation, the data burst is sent from the adapter to the controller and for a read operation the data burst is sent from the controller to the adapter. The sampling clock always travels with the parameters and data.

Abstract: The memory control subsystem controls and arbitrates access to a memory shared by a plurality of users. A processor with its cache and input/output devices has direct access to the memory through a direct memory access bus.The controls subsystem comprises a processor controller, a DMA controller and a memory controller.A processor request is buffered into the processor controller and is serviced immediately if the memory controller is available. A simultaneous transfer between the devices and buffers in the DMA controller is possible. If the memory controller is busy, the DMA controller causes the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards.Write requests made by the processor are buffered into processor controller and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion.