Patents by Inventor Zhanfeng CAO

Zhanfeng CAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220406749
    Abstract: Disclosed are an electrical connection method for an electronic element, and a backlight module, a display panel, and a display apparatus which include an electronic element to which the electrical connection method is applied. The electrical connection method comprises: providing a driving back plane, wherein the driving back plane comprises multiple contact electrodes; forming an anti-oxidation protection film on the contact electrodes; coating a position of the anti-oxidation protection film corresponding to each contact electrode with a binding material; and transferring multiple electronic elements to the positions of the corresponding contact electrodes, binding each electronic element to the corresponding contact electrode, and removing the anti-oxidation protection film at the position of each contact electrode before completing the binding of each electronic element to the corresponding contact electrode.
    Type: Application
    Filed: February 28, 2020
    Publication date: December 22, 2022
    Inventors: Zhanfeng CAO, Jiushi WANG, Ke WANG, Guocai ZHANG, Junwei YAN, Yingwei LIU, Haitao HUANG, Guangcai YUAN
  • Patent number: 11532264
    Abstract: A driving backplane includes a base, electroplating electrodes and driving electrodes. The base has first through holes in a sub-pixel region. The electroplating electrodes are disposed in the sub-pixel region, and at least a portion of each electroplating electrode is disposed within a respective one of the first through holes. The driving electrodes are disposed in the sub-pixel region and on a first side of the base, and each driving electrode is connected to a respective one of the electroplating electrodes.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: December 20, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Ke Wang, Zhanfeng Cao
  • Patent number: 11520094
    Abstract: The present disclosure provides a polarizing device and a method for preparing the same, a display substrate, and a display device. The polarizing device includes: a base substrate, a metal wire grid, and an anti-reflection layer, in which the metal wire grid is arranged on the base substrate, the anti-reflection layer is arranged on the surface of the metal wire grid away from the base substrate, and the anti-reflection layer is a carbon film layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: December 6, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Shuilang Dong, Da Lu, Qingzhao Liu, Guoqiang Wang, Zhanfeng Cao, Jiushi Wang
  • Publication number: 20220384492
    Abstract: An array substrate having a light-emitting unit region, a bonding region, and a bending region located between the light-emitting unit region and the bonding region. The light-emitting unit region is configured to be provided with light-emitting units. The bonding region is configured to bond a control circuit. The array substrate includes a base substrate located in the light-emitting unit region and the bonding region, a first organic material layer, a metal intermediate layer, and a second organic material layer. The first organic material layer is disposed on a side of the base substrate. The metal intermediate layer is disposed on a side of the first to organic material layer away from the base substrate. The second organic material layer is disposed on a side of the metal intermediate layer away from the base substrate.
    Type: Application
    Filed: March 5, 2021
    Publication date: December 1, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xinhong LU, Zhanfeng CAO, Ke WANG, Jiushi WANG, Xiaoyan ZHU
  • Publication number: 20220376137
    Abstract: A light-emitting diode (LED) chip includes a plurality of epitaxial structures, at least one first electrode, and a plurality of second electrodes. Any two adjacent epitaxial structures of the plurality of epitaxial structures have a gap therebetween. Each epitaxial structure includes a first semiconductor pattern, a light-emitting pattern and a second semiconductor pattern stacked in sequence. First semiconductor patterns in at least two of the plurality of epitaxial structures are connected to each other to form a first semiconductor layer. A first electrode is electrically connected to the first semiconductor layer. Each second electrode is electrically connected to the second semiconductor pattern in at least one of the plurality of epitaxial structures.
    Type: Application
    Filed: November 6, 2020
    Publication date: November 24, 2022
    Inventors: Mingxing WANG, Binbin TONG, Lizhen ZHANG, Chenyang ZHANG, Zhen ZHANG, Xiawei YUN, Guangcai YUAN, Xue DONG, Muxin DI, Zhiwei LIANG, Ke WANG, Zhanfeng CAO
  • Publication number: 20220375966
    Abstract: An array substrate includes a base substrate, a driving circuit layer, and a functional device layer which are sequentially stacked; the driving circuit layer is provided with first driving circuits, and each first driving circuit at least comprises a driving transistor; and the driving circuit layer comprises a first gate layer, a first gate insulation layer, a semiconductor layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer which are sequentially stacked on one side of the base substrate.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Xue DONG, Guangcai YUAN, Ce NING, Zhiwei LIANG, Feng GUAN, Zhaohui QIANG, Yingwei LIU, Ke WANG, Zhanfeng CAO
  • Patent number: 11495718
    Abstract: The present disclosure provides a driving substrate, a method for preparing the same, and a flexible display device. The driving substrate includes: a base substrate; a first driving function layer arranged on a first surface of the base substrate, the first driving function layer including a plurality of driving thin film transistors and a plurality of signal wirings, and at least one of the plurality of signal wirings being of a single-layer structure and having a thickness greater than a threshold; a pad layer arranged on a surface of the first driving function layer away from the base substrate, the pad layer including a plurality of first pads and a plurality of second pads, and each first pad being connected to a first electrode of the corresponding driving thin film transistor and each second pad being connected to a common electrode line in the plurality of signal wirings.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: November 8, 2022
    Assignee: Beijing Boe Technology Development Co., Ltd.
    Inventors: Zhanfeng Cao, Yingwei Liu, Ke Wang, Dongni Liu, Minghua Xuan, Guangcai Yuan, Lei Chen, Xue Dong
  • Patent number: 11495623
    Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. In the display substrate of the present disclosure, a first transistor comprises a first gate electrode, a first electrode, a second electrode, and a first active layer; and a second transistor comprises a second gate electrode, a third electrode, a fourth electrode, and a second active layers, wherein the first active layer comprises a silicon material, the second active layer comprises an oxide semiconductor material, and wherein the third electrode and the first gate electrode are disposed in the same layer, and the fourth electrode and the first electrode, the second electrodes are disposed in the same layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 8, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Yanan Niu, Kuanjun Peng, Jiushi Wang, Zhanfeng Cao, Feng Zhang, Qi Yao, Wusheng Li, Feng Guan, Lei Chen, Jintao Peng, Tingting Zhou
  • Publication number: 20220352000
    Abstract: A light-emitting diode substrate, a manufacturing method thereof, and a display device are disclosed. The manufacturing method of the light-emitting diode substrate includes: forming an epitaxial layer group of M light-emitting diode chips on a substrate; transferring N epitaxial layer groups on N substrates onto a transition carrier substrate, the N epitaxial layer groups on the N substrates being densely arranged on the transition carrier substrate; and transferring at least part of N*M light-emitting diode chips corresponding to the N epitaxial layer groups on the transition carrier substrate onto a driving substrate, an area of the transition carrier substrate is greater than or equal to a sum of areas of the N substrates, M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 2.
    Type: Application
    Filed: October 30, 2020
    Publication date: November 3, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Haixu LI, Xiao ZHANG, Fei WANG, Mingxing WANG, Shulei LI, Xue DONG, Guangcai YUAN, Zhanfeng CAO, Xin GU, Ke WANG, Feng QU, Xuan LIANG, Junwei YAN
  • Patent number: 11488987
    Abstract: The disclosure relates to the technical field of display devices and discloses a display substrate, a splicing screen and a manufacturing method thereof. The display substrate includes a flexible substrate; a plurality of signal lines located at one side of the flexible substrate; a plurality of plating electrodes located at one side of the signal lines toward the flexible substrate and electrically connected to the signal lines in one-to-one correspondence; a plurality of first through holes in one-to-one correspondence to the plating electrodes and penetrating the flexible substrate and exposing the plating electrodes, the first through roles being filled with a conductive material inside; and a plurality of binding electrodes located at one side of the flexible substrate away from the signal lines and in one-to-one correspondence to the first through holes, the binding electrodes being electrically connected to corresponding plating electrode through conductive material in corresponding first through hole.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 1, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Yingwei Liu, Shuang Liang, Zhiwei Liang, Muxin Di, Ke Wang, Zhanfeng Cao
  • Publication number: 20220344557
    Abstract: The present disclosure provides a display backplane including an array substrate including at least one pixel unit each including at least one TFT; a planarization layer covering the array substrate; a pad layer including pads on the planarization layer, surface of the pad away from the planarization layer being first surface, each pixel unit being provided with one pad electrically coupled to a driving thin film transistor in a corresponding pixel unit through via hole penetrating through the planarization layer; a passivation layer covering the pad layer and including through holes, each pad corresponding to one through hole, such that the first surface of each pad is exposed through corresponding through hole, and area of top opening of through hole is smaller than area of bottom opening thereof. The present disclosure further provides a fabrication method of the display backplane, a display panel and a fabrication method thereof.
    Type: Application
    Filed: October 22, 2020
    Publication date: October 27, 2022
    Inventors: Haixu LI, Guangcai YUAN, Zhanfeng CAO, Ke WANG, Qi QI
  • Publication number: 20220344554
    Abstract: The present disclosure relates to a backplane, a backlight source, a display device, and a manufacturing method of the backplane. The backplane includes: a substrate; a plurality of barriers disposed on a surface of the substrate; and a first metal layer disposed on the surface of the substrate and including a plurality of metal patterns spaced apart by the plurality of barriers, wherein the barrier and the metal pattern are connected by a concave-convex mating structure.
    Type: Application
    Filed: August 30, 2019
    Publication date: October 27, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ke WANG, Zhanfeng CAO
  • Patent number: 11469261
    Abstract: An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 11, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Shengguang Ban, Zhanfeng Cao, Ke Wang, Qingzhao Liu, Shuilang Dong
  • Publication number: 20220310660
    Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a backlight module. The manufacturing method of the array substrate includes: providing a base substrate; forming a metal wiring layer on a side of the base substrate, the metal wiring layer including a first copper metal layer; forming a planarization layer on a side of the metal wiring layer away from the base substrate; forming a drive lead layer on a side of the planarization layer away from the base substrate, the drive lead layer being electrically connected to the metal wiring layer, the drive lead layer including a second copper metal layer with a thickness larger than that of the first copper metal layer; forming a functional device layer on a side of the drive lead layer away from the base substrate.
    Type: Application
    Filed: September 18, 2020
    Publication date: September 29, 2022
    Inventors: Zhanfeng CAO, Ke WANG, Zhiwei LIANG, Jianguo WANG, Guocai ZHANG, Xinhong LU, Qi QI
  • Publication number: 20220302234
    Abstract: A display substrate is provided, which includes a base substrate and a plurality of sub-pixels disposed on the base substrate. At least one sub-pixel includes a light transmittance region and a display region. The display region includes a circuit structure layer and a light-emitting element which are disposed on a base substrate, and the light-emitting element is connected with the circuit structure layer. The display substrate further includes a plurality of insulating layers disposed on the base substrate, and at least one insulating layer is hollowed out in the light transmittance region.
    Type: Application
    Filed: October 15, 2021
    Publication date: September 22, 2022
    Inventors: Dapeng XUE, Shuilang DONG, Ke WANG, Zhanfeng CAO
  • Publication number: 20220302177
    Abstract: A substrate includes: a base substrate; an organic layer on the base substrate with openings defined through the organic layer; a first metal layer including first metal patterns, where the first metal pattern is in the opening, and includes a first portion parallel to a bottom of the opening and a second portion parallel to a lateral wall of the opening; a second metal layer having a thickness greater than a thickness of the first metal layer; where the second metal layer includes second metal patterns, the second metal pattern is located in the opening and is in contact with the first metal layer; and, a distance from a surface of the first metal layer away from the base substrate to a plane where the base substrate is located is smaller than a distance from a surface of the organic layer away from the base substrate to the plane.
    Type: Application
    Filed: December 14, 2021
    Publication date: September 22, 2022
    Inventors: Yingwei LIU, Zhanfeng CAO, Ke WANG, Guocai ZHANG, Junwei YAN
  • Publication number: 20220293018
    Abstract: The present application discloses an array substrate and a splicing screen. The array substrate provided by an embodiment of the present application includes: a flexible base, wherein the flexible base includes a display region, a first region and a second region, the display region and at least one of the first region and the second region are located in different planes, and the first region is located between the display region and the second region; a plurality of signal lines, arranged on the display region and the first region; a plurality of fan-out lines, arranged on the second region and connected with the plurality of signal lines in a one-to-one correspondence; and a buffer cushion, arranged on the first region, wherein an orthographic projection of the buffer cushion on the flexible base does not overlap with orthographic projections of the signal lines on the flexible base.
    Type: Application
    Filed: October 22, 2021
    Publication date: September 15, 2022
    Inventors: Shuilang DONG, Xinhong LU, Jingshang ZHOU, Lei ZHAO, Zhanfeng CAO, Dapeng XUE, Lizhong WANG, Guangcai YUAN
  • Publication number: 20220293635
    Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a plurality of chips arranged on the base substrate each including a chip main body and a plurality of terminals arranged thereon; a plurality of fixed connection portions arranged on the base substrate, and adjacent to the plurality of chips; a terminal expansion layer arranged on the base substrate; and a plurality of expansion wires in the terminal expansion layer and configured to electrically connect the chips, wherein an expansion wire configured to electrically connect two chips includes at least a first wire segment and a second wire segment, and the first wire segment is configured to electrically connect a terminal of a chip and a fixed connection portion adjacent to the chip, and the second wire segment is configured to connect two fixed connection portions between the two chips.
    Type: Application
    Filed: November 18, 2021
    Publication date: September 15, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chenyang Zhang, Fuqiang Li, Xue Dong, Meili Wang, Xuan Liang, Fei Wang, Mingxing Wang, Zhanfeng Cao, Yanling Han, Xinxin Zhao
  • Publication number: 20220293576
    Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a chip arranged on the base substrate, wherein the chip includes a chip main body and a plurality of terminals arranged on the chip main body; a terminal expansion layer arranged on the base substrate, the terminal expansion layer including a conductive material, and the terminal expansion layer and at least one terminal are located on a same side of the chip main body; and a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are electrically connected to the plurality of terminals, respectively, to lead out the plurality of terminals, wherein an orthographic projection of at least one expansion wire on the base substrate completely covers an orthographic projection of a terminal electrically connected to the expansion wire on the base substrate.
    Type: Application
    Filed: November 29, 2021
    Publication date: September 15, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Meili Wang, Xuan Liang, Fei Wang, Lei Wang, Yafeng Yang, Xue Dong, Zhanfeng Cao, Mingxing Wang, Fuqiang Li, Chenyang Zhang, Xinxin Zhao, Yanling Han, Lei Wang, Xuan Feng, Yapeng Li
  • Patent number: 11437265
    Abstract: The present disclosure discloses a mass transfer method and system for micro light emitting diodes, wherein the mass transfer method includes: providing a component substrate on which a plurality of micro light emitting diodes are formed; picking up the micro light emitting diodes on the component substrate at least once by a plurality of bonding structures on a first medium load substrate, and transferring micro light emitting diodes picked up every time to a second medium load substrate; and transferring the micro light emitting diodes on the second medium load substrate into corresponding sub-pixels on a target substrate at one time, wherein one of the micro light emitting diodes on the second medium load substrate corresponds to one of the sub-pixels on the target substrate.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 6, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Xue Dong, Guangcai Yuan, Zhijun Lv, Haixu Li, Zhiwei Liang, Huijuan Wang, Ke Wang, Zhanfeng Cao, Hsuanwei Mai