Patents by Inventor Zhenming Zhou

Zhenming Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10825513
    Abstract: A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 3, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta, Zhenming Zhou
  • Publication number: 20200321060
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Patent number: 10790036
    Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. A plurality of test demarcation voltages is determined based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell. For each test demarcation voltage, an error rate of reading the state of the memory cell based on a respective test demarcation voltage is determined. A test demarcation voltage having the lowest error rate from the plurality of test demarcation voltages is determined. The current demarcation voltage is set to correspond to the test demarcation voltage having the lowest error rate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Murong Lang
  • Patent number: 10726925
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Patent number: 10636498
    Abstract: A non-volatile memory system comprises a plurality of word lines, a plurality of bit lines, non-volatile memory cells, and a sensing circuit. The sensing circuit is configured to sense a first set of the memory cells coupled to a contiguous set of the bit lines and a selected word line using a first bit line settling time. The sensing circuit is configured to sense a second set of the memory cells coupled to a non-contiguous set of the bit lines and the selected word line using a second bit line settling time.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Xiang Yang, Zhenming Zhou, Deepanshu Dutta
  • Publication number: 20200098434
    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Murong Lang, Zhenming Zhou, Deepanshu Dutta
  • Patent number: 10541038
    Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Xiang Yang, Zhenming Zhou, Deepanshu Dutta, Huai-Yuan Tseng
  • Publication number: 20190392894
    Abstract: A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta, Zhenming Zhou
  • Publication number: 20190378583
    Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
    Type: Application
    Filed: November 29, 2018
    Publication date: December 12, 2019
    Inventors: Yu-Chung Lien, Xiang Yang, Zhenming Zhou, Deepanshu Dutta, Huai-Yuan Tseng
  • Publication number: 20190348127
    Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 14, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Henry Chin, Zhenming Zhou
  • Publication number: 20190348129
    Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 14, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Henry Chin, Zhenming Zhou
  • Patent number: 9805809
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for state-dependent read compensation. A set of non-volatile storage cells comprising a plurality of word lines. A controller is configured to perform a read operation on one or more word lines adjacent to a target word line. A controller is configured to determine a read setting for application to a target word line based on a result of a read operation on one or more word lines adjacent to the target word line. A controller is configured to perform a read operation on a target word line using a determined read setting.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenming Zhou, Guirong Liang, Gerrit Jan Hemink, Dana Lee, Chandu Gorla, Sarath Puthenthermadam, Deepanshu Dutta
  • Patent number: 9710325
    Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Wenzhou Chen, Zhenming Zhou, Jun Wan, Deepanshu Dutta, Yi-Chieh Chen, Dana Lee
  • Patent number: 9563504
    Abstract: Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Guirong Liang, Zhenming Zhou, Masaaki Higashitani
  • Patent number: 9564226
    Abstract: Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is saved. The smart verify may be used to characterize programming speed. Results of the smart verify may be used to determine a magnitude of a dummy program pulse to be applied later in the programming process. The dummy program pulse is not followed by a program verify, which reduces current. If the dummy program pulse pushes threshold voltages high enough, then those memory cells will not conduct a current when verifying later in programming. Thus, current is saved during the program verify. Also, bit lines of memory cells that received the dummy pulses do not need to be pre-charged prior to a program pulse, which can save more current.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 7, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Mohan Dunga, Gerrit Jan Hemink, Zhenming Zhou, Masaaki Higashitani
  • Patent number: 9548124
    Abstract: A memory device includes memory cells arranged in word lines. Due to variations in the fabrication process, with width and spacing between word lines can vary, resulting in widened threshold voltage distributions. In one approach, a programming parameter is optimized for each word line based on a measurement of the threshold voltage distributions in an initial programming operation. An adjustment to the programming parameter of a word line can be based, e.g., on measurements from adjacent word lines, and a position of the word line in a set of word lines. The programming parameter can include a programming mode such as a number of programming passes. Moreover, the programming parameters from one set of word lines can be used for another set of word lines having a similar physical layout due to the variations in the fabrication process.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 17, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Arash Hazeghi, Gerrit Jan Hemink, Dana Lee, Henry Chin, Bo Lei, Zhenming Zhou
  • Patent number: 9530517
    Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Aaron Lee, Zhenming Zhou, Mrinal Kochar, Cynthia Hua-Ling Hsu
  • Patent number: 9530504
    Abstract: A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes using a four-pass programming technique to program a block of the non-volatile memory cells.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Bo Lei, Gerrit Jan Hemink, Masaaki Higashitani, Jun Wan, Zhenming Zhou
  • Publication number: 20160343449
    Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Aaron Lee, Zhenming Zhou, Mrinal Kochar, Cynthia Hua-Ling Hsu
  • Patent number: 9460799
    Abstract: Techniques for recovery of partially programmed blocks in non-volatile storage are disclosed. After programming memory cells in an open region of a partially programmed block, a fail bit count with respect to programming the memory cells is performed. If the fail bit count is above a threshold, then a recovery operation is performed of other memory cells in the partially programmed block. The recovery operation (such as erase) may remove charges that are trapped in the tunnel dielectric of memory cells in the open region of the partially programmed block. Note that this erase operation may be performed on memory cells in the open region that are already erased. The erase operation may remove trapped charges from the tunnel dielectric. In a sense, this “resets” the memory cells. Thus, the memory cells can now be programmed more effectively. Both programming and date retention may be improved.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 4, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Xiying Costa, Dana Lee, Zhenming Zhou