Patents by Inventor Zhenyu Lu
Zhenyu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230083030Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: November 10, 2022Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
-
Publication number: 20230084008Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.Type: ApplicationFiled: September 13, 2021Publication date: March 16, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
-
Publication number: 20230070357Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.Type: ApplicationFiled: August 15, 2022Publication date: March 9, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Lidong SONG, Yongna LI, Feng PAN, Xiaowang DAI, Dan LIU, Steve Weiyi YANG, Simon Shi-Ning YANG
-
Patent number: 11599586Abstract: A computing device hosting a website of a business may be operable to receive a first search input comprising a term submitted via a search bar on the website. Upon performing an internal search for the term with no result, the computing device may output information on the no-result. The computing device may then perform, using one or more external search engines, a search for the term. Search results of the search, performed using the external search engine(s), may be analyzed. Based on a result of the analysis, one or more particular character strings related to the term may be identified. The computing device may generate and store, based on the identifying of the particular character string(s), one or more alternative search suggestions. Upon subsequently receiving an input comprising at least a portion of the term entered in the search bar, the computing device may output the alternative search suggestion(s).Type: GrantFiled: November 3, 2020Date of Patent: March 7, 2023Assignee: TRANSFORM SR BRANDS LLCInventors: Rongkai Zhao, Zhenyu Lu, Kenneth Katschke
-
Publication number: 20230016627Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Publication number: 20230005950Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating dielectric stack comprising a plurality of dielectric layer pairs arranged in a vertical direction; n alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs arranged in the vertical direction; and at least one through array contact extending through the alternating dielectric stack in the vertical direction; a barrier structure separates the alternating dielectric stack and the alternating conductor/dielectric stack, an opening of the barrier structure is at an edge of the alternating dielectric stack along a lateral direction, the lateral direction is perpendicular to the vertical direction.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Wenguang SHI, Guanping WU, Xianjin WAN, Baoyou CHEN
-
Patent number: 11545505Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.Type: GrantFiled: January 6, 2021Date of Patent: January 3, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
-
Patent number: 11527547Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure including two parallel barrier walls extending vertically through the alternating layer stack and laterally along a word line direction to laterally separate the first region from the second region. The memory device further comprises a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack.Type: GrantFiled: January 13, 2021Date of Patent: December 13, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Simon Shi-Ning Yang, Feng Pan, Steve Weiyi Yang, Jun Chen, Guanping Wu, Wenguang Shi, Weihua Cheng
-
Patent number: 11482532Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: GrantFiled: November 18, 2020Date of Patent: October 25, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Patent number: 11462474Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: April 17, 2019Date of Patent: October 4, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
-
Publication number: 20220238556Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: ApplicationFiled: April 19, 2022Publication date: July 28, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
-
Patent number: 11380701Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: December 17, 2020Date of Patent: July 5, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
-
METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF
Publication number: 20220208677Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.Type: ApplicationFiled: March 14, 2022Publication date: June 30, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng ZHU, Jun CHEN, Si Ping HU, Zhenyu LU -
Publication number: 20220181483Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.Type: ApplicationFiled: February 23, 2022Publication date: June 9, 2022Applicant: Micron Technology, Inc.Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
-
Patent number: 11309327Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: GrantFiled: July 26, 2018Date of Patent: April 19, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
-
Patent number: 11289611Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.Type: GrantFiled: April 10, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
-
Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof
Patent number: 11276642Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.Type: GrantFiled: August 18, 2020Date of Patent: March 15, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu -
Patent number: 11271004Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.Type: GrantFiled: December 14, 2020Date of Patent: March 8, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
-
Patent number: 11264397Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.Type: GrantFiled: September 21, 2020Date of Patent: March 1, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
-
Patent number: 11211397Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.Type: GrantFiled: July 27, 2018Date of Patent: December 28, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang