Patents by Inventor Zhi-Cheng Lee
Zhi-Cheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10014406Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.Type: GrantFiled: August 16, 2016Date of Patent: July 3, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Yu-Hao Huang, Kai-Lin Lee
-
Publication number: 20180166574Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first epitaxial layer adjacent to two sides of the gate structure; forming a patterned mask on the epitaxial layer; and using the patterned mask to remove part of the first epitaxial layer for forming a second epitaxial layer.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Chih-Chun Hu
-
Publication number: 20180012992Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.Type: ApplicationFiled: August 16, 2016Publication date: January 11, 2018Inventors: Zhi-Cheng Lee, Yu-Hao Huang, Kai-Lin Lee
-
Patent number: 9640661Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a fin-shaped structure is formed on the substrate. Next, a gate structure is formed on the fin-shaped structure, and an epitaxial layer is formed adjacent to the gate structure. Preferably, the epitaxial layer includes a V-shaped profile viewing from the top. According to the preferred embodiment of the present invention, the V-shaped profile of the epitaxial layer allows more stress to be applied to the region having concentrated currents or edges of the fin-shaped structures during an on-state, and at the same time prevent exerting too much stress to the region having high currents or central region of the fin-shaped structure during an off-state.Type: GrantFiled: May 3, 2016Date of Patent: May 2, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Yu-Hao Huang
-
Patent number: 9490342Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.Type: GrantFiled: June 16, 2011Date of Patent: November 8, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ming Lai, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
-
Patent number: 9384962Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: GrantFiled: April 7, 2011Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
-
Publication number: 20140339652Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
-
Patent number: 8802524Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.Type: GrantFiled: March 22, 2011Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
-
Patent number: 8492259Abstract: A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.Type: GrantFiled: August 16, 2012Date of Patent: July 23, 2013Assignee: United Microelectronics Corp.Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
-
Patent number: 8486842Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.Type: GrantFiled: October 8, 2010Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
-
Publication number: 20120319179Abstract: A metal gate includes a substrate, a gate dielectric layer, a work function metal layer, an aluminum nitride layer and a stop layer. The gate dielectric layer is located on the substrate. The work function metal layer is located on the gate dielectric layer. The aluminum nitride layer is located on the work function metal layer. The stop layer is located on the aluminum nitride layer.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Inventors: Hsin-Fu Huang, Zhi-Cheng Lee, Chi-Mao Hsu, Chin-Fu Lin, Kun-Hsien Lin, Tzung-Ying Lee, Min-Chuan Tsai
-
Publication number: 20120322218Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ming LAI, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
-
Publication number: 20120309185Abstract: A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.Type: ApplicationFiled: August 16, 2012Publication date: December 6, 2012Inventors: Che-Hua HSU, Shao-Hua HSU, Zhi-Cheng LEE, Cheng-Guo CHEN
-
Publication number: 20120256276Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
-
Publication number: 20120244669Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.Type: ApplicationFiled: March 22, 2011Publication date: September 27, 2012Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
-
Patent number: 8268712Abstract: A method of forming metal gate transistor includes providing a substrate; forming a gate dielectric layer, a work function metal layer and a polysilicon layer stacked on the substrate; forming a hard mask and a patterned photoresist on the polysilicon layer; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the work function metal layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.Type: GrantFiled: May 27, 2010Date of Patent: September 18, 2012Assignee: United Microelectronics CorporationInventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
-
Patent number: 8252515Abstract: A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed.Type: GrantFiled: October 13, 2009Date of Patent: August 28, 2012Assignee: United Microelectronics Corp.Inventors: Chin-Cheng Chien, Chan-Lon Yang, Chiu-Hsien Yeh, Che-Hua Hsu, Zhi-Cheng Lee, Shao-Hua Hsu, Cheng-Guo Chen, Shin-Chi Chen, Zhi-Jian Wang
-
Patent number: 8232152Abstract: A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.Type: GrantFiled: September 16, 2010Date of Patent: July 31, 2012Assignee: United Microelectronics Corp.Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen, Shin-Chi Chen, Hung-Ling Shih, Hung-Yi Wu, Heng-Ching Huang
-
Publication number: 20120142157Abstract: The method of fabricating a semiconductor structure according to the present invention includes planarizing an inter-layer dielectric layer and further a hard mask to remove a portion of hard mask in a thickness direction. The remaining hard mask has a thickness less than the original thickness of the hard mask. The remaining hard mask and the dummy gate are removed to form a recess. After a gate material is filled into the recess, a gate with a relatively accurate height can be obtained.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Inventors: Cheng-Guo Chen, Zhi-Cheng Lee, Shao-Hua Hsu, Jung-Tsung Tseng, Chien-Ting Lin, Cheng-Hsien Chou
-
Publication number: 20120088368Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen