Abstract: A staggered and crossed heat storage adsorption bed and a seawater desalination waste heat storage system are provided, which relate to the field of seawater desalination and the technical field of thermochemical adsorption heat storage. The adsorption bed includes a bed body, wherein an adsorption cavity is arranged in the bed body; two sides of the adsorption cavity are respectively communicated with an inlet cavity and an outlet cavity; the adsorption cavity includes a vacuum heat insulation layer arranged at an outermost side; the vacuum heat insulation layer is embedded with an adsorption box fixing layer; a corner end adsorption box, a central adsorption box and a side adsorption box are staggered and crossed arranged in an inner cavity of the vacuum heat insulation layer through the adsorption box fixing layer.

Abstract: Disclosed is a data analysis-based intelligent deformation monitoring system for mountain landslides, which solves the technical problem in the prior art that when a landslide occurs in a landslide area, it is not possible to implement region-specific monitoring for landslide soil, thus failing to minimize the real-time impact of the landslide area. The present disclosure involves marking a sub-area where a landslide occurs as a landslide area, marking a real-time sliding direction within the landslide area as a landslide flow direction, setting areas at both sides of the landslide flow direction as landslide slopes, generating a control adjustment signal or a risk monitoring signal through landslide slope analysis, and sending the signal to a server.

Abstract: Disclosed is a device for efficiently recycling nickel from wastewater and a method. The device includes a housing, and an extraction unit and an electro-deposition unit which are respectively arranged inside the housing. The device is reasonable in overall structural design. An oscillating and floating component and a rotating component in an extraction cavity are used to fully and uniformly mix a solution to maximize the extraction strength. A mixing component in an electro-deposition cavity is used to accelerate ion dispersion, to better recycle nickel. The device is easy to operate, low in cost and suitable for mass promotion.

Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Abstract: The photovoltaic module includes multiple cell sheets arranged in an array including multiple rows and multiple columns. Each of the multiple rows of cell sheets is arranged at intervals along a first direction, each of the multiple columns of cell sheets is arranged at intervals along a second direction. The photovoltaic module includes multiple support plates arranged at intervals, where each of the multiple support plates extends along a direction in which each of the multiple rows or multiple columns of cell sheets is arranged, and each of the multiple support plates is arranged on the second surface of each of the multiple rows or the multiple columns of cell sheets. The photovoltaic module further includes a first flexible cover layer arranged on a side of the first surface of each of the multiple cell sheets and a second flexible cover layer arranged on each of the multiple support plates.

Abstract: The photovoltaic module includes multiple cell sheets arranged in an array including multiple rows and multiple columns, where each of the multiple rows of cell sheets is arranged at intervals along a first direction, each of the multiple columns of cell sheets is arranged at intervals along a second direction, and each of the multiple cell sheets has a first surface and a second surface. The photovoltaic module further includes a first flexible cover layer located on a side of the first surface of each of the multiple cell sheets, and a second flexible cover layer located on a side of the second surface of each of the multiple cell sheets. The photovoltaic module is configured to be folded along a gap between two adjacent rows of cell sheets or along a gap between two adjacent columns of cell sheets with the folding angle of 0 degree to 180 degrees.

Abstract: A multi-degree-of-freedom continuum robot with a flexible target grasping function comprises a driving device module, a trunk simulation module and a nimble finger module. The trunk simulation module is composed of a rotary compression module and a bending compression module. Each module has a unified connection interface reserved at the end, and is combined and assembled according to actual needs. The driving module is arranged on the base of the robot to realize the driving operation of all cables to control the motion of the robot. The rotary compression module can simultaneously generate the motion in the forms of rotation and compression, thereby compensating for the defect of blind angle of the bending compression module. The bending compression module can realize compression deformation and bending deformation of the module independently. The nimble finger module realizes a grasping function by multi-finger collaboration.

Abstract: The present disclosure provides a chip packaging method and a chip packaging structure. The chip packaging method includes: providing an encapsulated grain and a packaging substrate, the encapsulated grain including a first hybrid bonding structure; wherein the packaging substrate includes a front side and a back side opposite to each other; a second hybrid bonding structure is formed on the front side of the packaging substrate and a connection pin is formed on the back side of the packing substrate; the second hybrid bonding structure and the connection pin are electrically connected through a third connecting metal column penetrating the packaging substrate; and bonding together the first hybrid bonding structure of the encapsulated grain and the second hybrid bonding structure of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate.

Abstract: A container group scheduling method includes obtaining multiple to-be-scheduled pods from a pod scheduling queue. Equivalence class partitioning on the multiple to-be-scheduled pods is performed to obtain at least one pod set. Each of the at least one pod set is determined as a target pod set. Scheduling processing is performed on the target pod set to bind each pod in the target pod set to a node configured to run the pod. A target schedulable node set corresponding to the target pod set is determined. A correspondence between the target pod set and the target schedulable node set is cached. From the target schedulable node set, a node corresponding to each pod in the target pod set is determined. Each pod in the target pod set is bound to the node corresponding to each pod in the target pod set. The cached correspondence is deleted.

Abstract: A multi-layer circuit board, successively constituted by surface sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, surface sticking layer, said multi-layer circuit board is provided with a hole, a hole wall of said hole is formed with conductive seed layer, and partial outer surface of said surface sticking layer is formed with a circuit pattern layer of conductive seed layer, wherein said conductive seed layer comprises a ion implantation layer implanting below the hole wall of said hole and below partial outer surface of said surface sticking layer.

Abstract: The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

Abstract: The present invention relates to a manufacturing apparatus and a manufacturing method for microwave means. The manufacturing apparatus (1) for microwave means comprises: a fixture (10, 10?), the fixture (10, 10?) comprising a base (11) capable of rotating about a first axis (A1), and a carrier (12) capable of swinging about a second axis (A2), the carrier (12) being connected to the base (11) so as to hold an insulating substrate (40), wherein the first axis (A1) intersects the second axis (A2); a source (20) for releasing metal ions towards the insulating substrate (40); and a controller (30), the controller (30) coupled to the fixture (10, 10?) and the source (20) and configured to control a movement pattern of the fixture (10, 10?) and/or an angle of the source (20) such that the insulating substrate (40) receives the metal ions from a plurality of angles and a metal layer (50) is formed over all surfaces (41) of the insulating substrate (40).

Abstract: The present application discloses a semi-floating gate memory device, which is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer, a source region and a drain region are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. The present application further discloses a method for fabricating the semi-floating gate memory device.

Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

Abstract: The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Abstract: A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.