Abstract: An apparatus and method for ultra wideband (UWB) communication, using a dual band pass filter (BPF) is disclosed. The UWB communication apparatus may include a first BPF performing a first band pass filtering with respect to a UWB signal, a second BPF that has a center frequency differing from a center frequency of the first BPF, and performs a second band pass filtering with respect to the UWB signal, a first envelope detector that detects a size of a first signal filtered in the first BPF, a second envelope detector that detects a size of a second signal filtered in the second BPF, and a demodulator that demodulates a UWB signal, using the size of the first signal and the size of the second signal.

Abstract: The present invention relates to the technical field of the human computer interaction, more particularly to, a system and method for human computer interaction. The system for human computer interaction comprises a projection unit, a first image sensing unit, a second image sensing unit, an interface unit, an image processing unit, a projected interface processing unit, and a controlling unit. The system for human computer interaction provided by the present invention may easily project the human computer interaction interface on all kinds of planes encountered in people's daily life, to realize display of the human computer interaction interface everywhere, and improve users' experience.

Abstract: A receiver, an operating method of the receiver, and a beamforming radar system including the receiver are provided. A beamforming receiver may include a demodulation circuit configured to receive a signal reflected from an object via an antenna, to demodulate the received signal, and to generate a demodulated signal, and a time delay circuit configured to generate a digital signal by processing the demodulated signal based on reference clock signals, wherein the digital signal including static delay information associated with a static motion of the object, and dynamic delay information associated with a dynamic motion of the object.

Abstract: The present invention provides a one-dimensional global rainbow measurement device and a measurement method. The measurement device comprises three parts, i.e., a laser emission unit, a signal collection unit and a signal processing unit. The laser emission unit is modulated to be a light sheet by a laser beam emitted by a laser, and configured to irradiate droplets in a spray field to generate rainbow signals. The signal collection unit is configured to separately image, by an optical system unit, the rainbow signals at measurement points of different height onto different row pixels of a CCD signal collector. The signal processing unit is configured to convert the received rainbow signals and process by a computer the rainbow signals in a form of data to obtain the measured values.

Abstract: A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses.

Abstract: The present invention relates to a method for displaying fault problems. The method comprises: detecting a computer, to find fault problems of the computer among fault problems supported by a computer fault diagnosing and treating program; sorting the fault problems supported by the computer fault diagnosing and treating program, wherein the detected fault problems of the computer are preferentially sorted; and sequentially displaying the fault problems supported by the computer fault diagnosing and treating program. The present invention also provides a corresponding system for displaying fault problems. By means of the method and the system for displaying fault problems according to the present invention, the fault problems most expected to be solved can be easily and quickly found in display result.

Abstract: The invention discloses a power grid fault ride-through device and a method for a doubly fed induction generator.

Abstract: An apparatus and method for ultra wideband (UWB) communication, using a dual band pass filter (BPF) is disclosed. The UWB communication apparatus may include a first BPF performing a first band pass filtering with respect to a UWB signal, a second BPF that has a center frequency differing from a center frequency of the first BPF, and performs a second band pass filtering with respect to the UWB signal, a first envelope detector that detects a size of a first signal filtered in the first BPF, a second envelope detector that detects a size of a second signal filtered in the second BPF, and a demodulator that demodulates a UWB signal, using the size of the first signal and the size of the second signal.

Abstract: A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses.

Abstract: A transmitter and a receiver for reducing power consumption in a frequency modulation-ultra-wideband (FM-UWB) communication system are provided. The transmitter includes a detector configured to generate a pulse signal when an edge of a digital signal is detected. The transmitter further includes a first modulator configured to modulate the digital signal into a first modulation signal based on a value of the digital signal. The transmitter further includes a second modulator configured to modulate the first modulation signal into a second modulation signal based on a frequency of the first modulation signal when the pulse signal is generated.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.

Abstract: A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals.

Abstract: The present invention discloses a method for transmitting parallelization signals of uninterruptible power supplies, which firstly performs a serialization process on parallelization signals by a logic processing unit and then performs synchronous transmission of the parallelization signals of respective node units over a bus. The method for serial transmission of parallelization signals of uninterruptible power supplies according to the invention can be implemented with easy wiring and can achieve a strong anti-interference ability, ensure real time signal transmission over a guaranteed transmission distance and identify conveniently the failure of a parallelization line while satisfying fundamental transmission demands.

Abstract: A bridge plug arrangement includes a plug having an upper end and a bottom end. The bridge plug arrangement also optionally includes a cylindrical seat. The bridge plug arrangement further includes a tubular member. The tubular member may be part of a casing string. The tubular member is configured to receive the plug and, when used, the seat. The plug and/or the seat may be fabricated from a frangible material. A method for diverting fluids in a wellbore using the bridge plug arrangement is also provided. The method may include landing the plug onto the seat within the wellbore below a subsurface zone of interest. Treatment fluids are then injected into the wellbore, where they are diverted through perforations and into a formation. The plug and/or seat is then optionally broken into a plurality of pieces through use of a downward mechanical force.

Abstract: The invention discloses a power grid fault ride-through device and a method for a doubly fed induction generator.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals.