Patents by Inventor Zhijong Luo

Zhijong Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150279993
    Abstract: A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: November 27, 2012
    Publication date: October 1, 2015
    Inventors: Huilong Zhu, Haizhou Yin, Zhijong Luo
  • Patent number: 8952429
    Abstract: The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: February 10, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijong Luo, Huilong Zhu
  • Patent number: 8828820
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 9, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Patent number: 8716800
    Abstract: Semiconductor structure and methods for manufacturing the same are disclosed.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 6, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijong Luo, Qingqing Liang
  • Publication number: 20130323894
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 5, 2013
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Patent number: 8564029
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: October 22, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Patent number: 8507958
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: August 13, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Patent number: 8399328
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 19, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijong Luo, Huilong Zhu
  • Publication number: 20120305941
    Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves.
    Type: Application
    Filed: July 26, 2011
    Publication date: December 6, 2012
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Patent number: 8299509
    Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Seong-Dong Kim, Zhijong Luo, Huilong Zhu
  • Publication number: 20120193531
    Abstract: A method for line width measurement, comprising: providing a substrate, wherein a raised line pattern is formed on a surface of the substrate, and the line pattern has a width; forming a first measurement structure and a second measurement structure on opposite sidewalls of the line pattern in the width direction of the line pattern; removing the line pattern; and measuring the spacing between the first measurement structure and the second measurement structure, and obtaining the width of the line pattern by subtracting a predetermined offset from the spacing. The present invention facilitates to reduce the uncertainty associated with the measuring process and to improve the measurement precision.
    Type: Application
    Filed: July 22, 2011
    Publication date: August 2, 2012
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Publication number: 20120168863
    Abstract: Semiconductor structure and methods for manufacturing the same are disclosed.
    Type: Application
    Filed: March 4, 2011
    Publication date: July 5, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijong Luo, Qingqing Liang
  • Publication number: 20120104473
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
    Type: Application
    Filed: May 20, 2011
    Publication date: May 3, 2012
    Applicant: Institute of Microelectornics, Chinese Academy of Sciences a Chinese Corporation
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Publication number: 20120104474
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.
    Type: Application
    Filed: May 20, 2011
    Publication date: May 3, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences a Chines Corporation
    Inventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
  • Publication number: 20120104486
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region.
    Type: Application
    Filed: May 19, 2011
    Publication date: May 3, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences, a Chinese Corporation
    Inventors: Haizhou Yin, Zhijong Luo, Huilong Zhu
  • Publication number: 20120061736
    Abstract: The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.
    Type: Application
    Filed: May 13, 2011
    Publication date: March 15, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijong Luo, Huilong Zhu
  • Publication number: 20110266677
    Abstract: The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises; providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.
    Type: Application
    Filed: September 19, 2010
    Publication date: November 3, 2011
    Inventors: Huilong Zhu, Haizhou Yin, Zhijong Luo