Patents by Inventor Zhijun Lei

Zhijun Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930159
    Abstract: Methods, articles, and systems of video coding use intra block copying with hash-based searches.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Jason Tanner, Zhijun Lei
  • Publication number: 20240067603
    Abstract: Biguanide compounds of formula where R1 comprises a cubanyl-substituted alkyl and R2 comprises a substituted or unsubstituted alkyl, and their use in the treatment of cancers and viral infections are described.
    Type: Application
    Filed: December 16, 2021
    Publication date: February 29, 2024
    Inventors: David A. POTTER, Zhijun GUO, Gunda GEORG, Kwon Ho HONG, Jianxun LEI, Elizabeth AMBROSE, Kris WHITE
  • Publication number: 20230360307
    Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 9, 2023
    Applicant: Intel Corporation
    Inventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
  • Patent number: 11676322
    Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Darrel Palke, Sherine Abdelhak, Jill Boyce, Varghese George, Scott Janus, Adam Lake, Zhijun Lei, Zhengmin Li, Mike Macpherson, Carl Marshall, Selvakumar Panneer, Prasoonkumar Surti, Karthik Veeramani, Deepak Vembar, Vallabhajosyula Srinivasa Somayazulu
  • Publication number: 20230037152
    Abstract: The disclosed computer-implemented method may include combining a first video sequence with a second video sequence to generate a combined video sequence. A video complexity of the first video sequence may differ from that of the second video sequence. The method may also include performing, using a baseline encoder, encoding parameter optimization on the combined video sequence to generate a baseline performance curve and performing, using a target encoder, encoding parameter optimization on the combined video sequence to generate a target performance curve. The method may further include analyzing the target encoder by comparing the target performance curve with the baseline performance curve, and generating a bitrate ladder for the target encoder based on the analysis, wherein the bitrate ladder includes desired bitrate-resolution pairs for encoding. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: February 4, 2022
    Publication date: February 2, 2023
    Inventors: Ping-Hao Wu, Ioannis Katsavounidis, Zhijun Lei
  • Patent number: 11323700
    Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Publication number: 20220109840
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to encode and decode video using quantization matrices. An example apparatus includes interface circuitry to access an input frame of video, quantization matrix syntax encoder circuitry to encode a set of user-defined quantization matrices into a sequence header associated with a sequence of video frames including the input frame, adaptive quantization matrix selector circuitry to select a subset of quantization matrices from a combination of a set of default quantization matrices and the set of user-defined quantization matrices, adaptive segment selector circuitry to select a first one of the subset of quantization matrices for a first segment of the input frame, the input frame to be divided into a plurality of segments including the first segment, and encoder circuitry to quantize transform coefficients of the first segment of the input frame based on the first one of the subset of quantization matrices.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 7, 2022
    Inventors: Ximin Zhang, Zhijun Lei, Jill Boyce, Sang-Hee Lee
  • Publication number: 20220086445
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for multi-symbol equiprobable mode entropy coding. An example apparatus includes equiprobable bypass control circuitry to determine whether an input value associated with the one or more blocks is greater than a reference value. The example apparatus also includes interval control circuitry to, based on the determination, adjust at least one of an upper limit or a lower limit based on an approximate value approximating a product of (1) a quotient of (a) a difference between the alphabet size and one and (b) the alphabet size and (2) the upper limit, the upper limit and the lower limit forming a range of values within which the input value is to be encoded.
    Type: Application
    Filed: November 30, 2021
    Publication date: March 17, 2022
    Inventors: Alexander Alshin, Jill Boyce, Zhijun Lei, Miroslav Goncharenko, Vasily Aristarkhov
  • Publication number: 20220058853
    Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
    Type: Application
    Filed: October 13, 2021
    Publication date: February 24, 2022
    Applicant: Intel Corporation
    Inventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
  • Patent number: 11151769
    Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Hugues Labbe, Darrel Palke, Sherine Abdelhak, Jill Boyce, Varghese George, Scott Janus, Adam Lake, Zhijun Lei, Zhengmin Li, Mike Macpherson, Carl Marshall, Selvakumar Panneer, Prasoonkumar Surti, Karthik Veeramani, Deepak Vembar, Vallabhajosyula Srinivasa Somayazulu
  • Publication number: 20210144377
    Abstract: Techniques related to video coding include content adaptive quantization that provides a selection between objective quality and subjective quality delta QP offsets.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Zhijun Lei, Ximin Zhang, Sang-hee Lee
  • Publication number: 20210105466
    Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Applicant: Intel Corporation
    Inventors: Brinda Ganesh, Nilesh Jain, Sumit Mohan, Faouzi Kossentini, Jill Boyce, James Holland, Zhijun Lei, Chekib Nouira, Foued Ben Amara, Hassene Tmar, Sebastian Possos, Craig Hurst
  • Publication number: 20210084294
    Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Patent number: 10951900
    Abstract: Speeding up small block intra-prediction in video coding is described herein. The system includes an encoder. The encoder is to execute intra-prediction by deriving a plurality of prediction angles, wherein the prediction angles are based on a video coding standard. The encoder is also to disable a prediction angle for a current block to eliminate a dependency on an immediate predecessor block.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Zhijun Lei, Jason Tanner, Satya N. Yedidi
  • Patent number: 10855983
    Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Patent number: 10645383
    Abstract: Techniques related to selecting constrained directional enhancement filters for video coding are discussed. Such techniques may include selecting subset of constrained directional enhancement filters for use by a frame based on a frame level quantization parameter of the frame such that only the subset is used for filtering the frame.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Sang-hee Lee, Zhijun Lei, Dmitry Ryzhov
  • Publication number: 20200099926
    Abstract: Methods, articles, and systems of video coding use intra block copying with hash-based searches.
    Type: Application
    Filed: November 29, 2019
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Jason Tanner, Zhijun Lei
  • Publication number: 20200051309
    Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 13, 2020
    Applicant: Intel Corporation
    Inventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
  • Publication number: 20190297344
    Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Applicant: INTEL CORPORATION
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
  • Patent number: 10397574
    Abstract: Systems and methods for determining quantization parameter (QP) for video coding. Embodiments may be particularly advantageous for strongly temporal correlated frames, such as for video conferencing applications. An initial QP for a frame of a video sequence may be modified based on a spatial complexity or a temporal complexity associated with the video frame, and/or based on an inter-predicted frame bitrate target cycle, as a function of whether the frame is intra- or inter-predicted. The inter-predicted frame bitrate target cycle includes a sequence of two or more inter-predicted frame bitrate targets that are assigned to the frame according to the inter-predicted frame bitrate target cycle. A reference frame for an inter-predicted frame may be selected based on the bitrate target associated with candidate reference frames. Initial QP of an inter-predicted frame with a scene change may be modified in a manner independent of an inter-predicted frame bitrate target cycle.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Sang-Hee Lee, Zhijun Lei