Patents by Inventor Zhixin Cui

Zhixin Cui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210007333
    Abstract: The present invention relates to a movable aquaculture platform suitable for offshore onboard cabin culture and open culture. The aquaculture platform includes a hull with a propulsion system and an onboard control system. A recess recessed downwards based on a plane of a main deck is provided between the front and rear of the hull. Both sides of the recess are formed into an open structure corresponding to double sides of the hull. The recess is provided with a closed cage. The cage and the recess together constitute an open culture cabin. An internal space of the cage is used for culture. The hull is provided with a closed culture cabin below the recess. The present invention can flexibly switch between an onboard closed cabin culture mode, an onboard open cage culture mode and a mixed mode thereof according to different working conditions.
    Type: Application
    Filed: May 28, 2020
    Publication date: January 14, 2021
    Applicant: Fishery Machinery and Instrument Research Institute, Chinese Academy of Fishery Sciences
    Inventors: Mingchao Cui, Hao Xu, Zhixin Chen, Jing Wang
  • Patent number: 10818542
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Publication number: 20200335518
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Ken Oowada
  • Patent number: 10809417
    Abstract: A three-dimensional analog simulation test system for gas-liquid countercurrent in an abandoned mine goaf includes a three-dimensional analog simulation device configured to simulate an analog environment of gas-liquid countercurrent in an abandoned mine goaf, a gas supply system, an automatic water pressure control system and a hydraulic loading system. The three-dimensional analog simulation device includes a reaction frame and a three-dimensional analog simulation chamber. The reaction frame includes a beam, a base and a column for connecting the beam and the base. The three-dimensional analog simulation chamber is arranged inside the reaction frame. The test system can be used to simulate the gas-liquid countercurrent in an abandoned mine goaf so as to study the evolution of water accumulation and gas enrichment in long-term abandonment of closed mines and the migration evolution rules of gas-liquid two-phase in abandoned mines with high gas density.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiyuan University of Technology
    Inventors: Guorui Feng, Chunwang Zhang, Zhixin Jin, Rui Gao, Shengyong Hu, Zhen Li, Jiaqing Cui, Cheng Song, Xiaohong Niu
  • Patent number: 10811058
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Zhixin Cui, Akio Nishida, Johann Alsmeier, Yan Li, Steven Sprouse
  • Publication number: 20200312706
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Publication number: 20200312875
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Application
    Filed: May 29, 2020
    Publication date: October 1, 2020
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Publication number: 20200303397
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Zhixin CUI, Kiyohiko SAKAKIBARA, Yanli ZHANG
  • Patent number: 10777575
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Yanli Zhang
  • Publication number: 20200286915
    Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
  • Publication number: 20200286917
    Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: Michimoto KAMINAGA, Zhixin CUI
  • Publication number: 20200286903
    Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
  • Publication number: 20200286875
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: Akio NISHIDA, Mitsuteru MUSHIGA, Zhixin CUI
  • Patent number: 10756106
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Michiaki Sano, Ken Oowada, Zhixin Cui
  • Patent number: 10741579
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Ken Oowada
  • Publication number: 20200251479
    Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 6, 2020
    Inventors: Kiyohiko SAKAKIBARA, Masaaki HIGASHITANI, Masanori TSUTSUMI, Zhixin CUI
  • Publication number: 20200251149
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Yanli ZHANG, Zhixin CUI, Akio NISHIDA, Johann ALSMEIER, Yan LI, Steven SPROUSE
  • Patent number: 10707233
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Fei Zhou, Raghuveer S. Makala
  • Patent number: 10700090
    Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
  • Patent number: 10700078
    Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang